A square wave signal capable of testing 10HZ~10MHZ; (2) the reference clock input by the circuit is 1HZ, and the measured value is output in the form of 8421BCD code; (3) the system has a reset key; (4) adopt the method of layering sub sub module and design with Verilog HDL; (5) write test simulation program.

8位数字显示的简易频率计\contral.v
8位数字显示的简易频率计\control_test.v
8位数字显示的简易频率计\counter.v
8位数字显示的简易频率计\counter_test.v
8位数字显示的简易频率计\lacth_test.v
8位数字显示的简易频率计\latch.v
8位数字显示的简易频率计\test_top.v
8位数字显示的简易频率计\top.v
8位数字显示的简易频率计\说明文档.docx
8位数字显示的简易频率计

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