Using Verilog language to achieve the modulus of 60 counters, compiled by qualified, using quarter2 and above can be used directly, and the use of sub block mode

cffsd\db\lab02.asm.qmsg
cffsd\db\lab02.asm_labs.ddb
cffsd\db\lab02.cbx.xml
cffsd\db\lab02.cmp.cdb
cffsd\db\lab02.cmp.hdb
cffsd\db\lab02.cmp.kpt
cffsd\db\lab02.cmp.logdb
cffsd\db\lab02.cmp.rdb
cffsd\db\lab02.cmp.tdb
cffsd\db\lab02.cmp0.ddb
cffsd\db\lab02.dbp
cffsd\db\lab02.db_info
cffsd\db\lab02.eco.cdb
cffsd\db\lab02.eds_overflow
cffsd\db\lab02.fit.qmsg
cffsd\db\lab02.fnsim.hdb
cffsd\db\lab02.fnsim.qmsg
cffsd\db\lab02.hier_info
cffsd\db\lab02.hif
cffsd\db\lab02.map.cdb
cffsd\db\lab02.map.hdb
cffsd\db\lab02.map.logdb
cffsd\db\lab02.map.qmsg
cffsd\db\lab02.pre_map.cdb
cffsd\db\lab02.pre_map.hdb
cffsd\db\lab02.psp
cffsd\db\lab02.rtlv.hdb
cffsd\db\lab02.rtlv_sg.cdb
cffsd\db\lab02.rtlv_sg_swap.cdb
cffsd\db\lab02.sgdiff.cdb
cffsd\db\lab02.sgdiff.hdb
cffsd\db\lab02.signalprobe.cdb
cffsd\db\lab02.sim.hdb
cffsd\db\lab02.sim.qmsg
cffsd\db\lab02.sim.rdb
cffsd\db\lab02.sim.vwf
cffsd\db\lab02.sld_design_entry.sci
cffsd\db\lab02.sld_design_entry_dsc.sci
cffsd\db\lab02.syn_hier_info
cffsd\db\lab02.tan.qmsg
cffsd\db\wed.zsf
cffsd\hex.v
cffsd\lab02.asm.rpt
cffsd\lab02.cdf
cffsd\lab02.done
cffsd\lab02.dpf
cffsd\lab02.fit.rpt
cffsd\lab02.fit.smsg
cffsd\lab02.fit.summary
cffsd\lab02.flow.rpt
cffsd\lab02.map.rpt
cffsd\lab02.map.smsg
cffsd\lab02.map.summary
cffsd\lab02.pin
cffsd\lab02.pof
cffsd\lab02.qpf
cffsd\lab02.qsf
cffsd\lab02.qws
cffsd\lab02.sim.rpt
cffsd\lab02.sof
cffsd\lab02.tan.rpt
cffsd\lab02.tan.summary
cffsd\lab02.v
cffsd\lab02.vwf
cffsd\db
cffsd

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