The data collection

EDA课程设计\day1\day_1.ppt
EDA课程设计\day1\DDS\PRJ\db\altsyncram_83a1.tdf
EDA课程设计\day1\DDS\PRJ\db\altsyncram_eja1.tdf
EDA课程设计\day1\DDS\PRJ\db\DDS.cbx.xml
EDA课程设计\day1\DDS\PRJ\db\DDS.cmp.rdb
EDA课程设计\day1\DDS\PRJ\db\DDS.cmp_merge.kpt
EDA课程设计\day1\DDS\PRJ\db\DDS.db_info
EDA课程设计\day1\DDS\PRJ\db\DDS.hier_info
EDA课程设计\day1\DDS\PRJ\db\DDS.hif
EDA课程设计\day1\DDS\PRJ\db\DDS.ipinfo
EDA课程设计\day1\DDS\PRJ\db\DDS.lpc.html
EDA课程设计\day1\DDS\PRJ\db\DDS.lpc.rdb
EDA课程设计\day1\DDS\PRJ\db\DDS.lpc.txt
EDA课程设计\day1\DDS\PRJ\db\DDS.map.ammdb
EDA课程设计\day1\DDS\PRJ\db\DDS.map.bpm
EDA课程设计\day1\DDS\PRJ\db\DDS.map.cdb
EDA课程设计\day1\DDS\PRJ\db\DDS.map.hdb
EDA课程设计\day1\DDS\PRJ\db\DDS.map.kpt
EDA课程设计\day1\DDS\PRJ\db\DDS.map.logdb
EDA课程设计\day1\DDS\PRJ\db\DDS.map.qmsg
EDA课程设计\day1\DDS\PRJ\db\DDS.map.rdb
EDA课程设计\day1\DDS\PRJ\db\DDS.map_bb.cdb
EDA课程设计\day1\DDS\PRJ\db\DDS.map_bb.hdb
EDA课程设计\day1\DDS\PRJ\db\DDS.map_bb.logdb
EDA课程设计\day1\DDS\PRJ\db\DDS.pre_map.hdb
EDA课程设计\day1\DDS\PRJ\db\DDS.pti_db_list.ddb
EDA课程设计\day1\DDS\PRJ\db\DDS.root_partition.map.reg_db.cdb
EDA课程设计\day1\DDS\PRJ\db\DDS.rpp.qmsg
EDA课程设计\day1\DDS\PRJ\db\DDS.rtlv.hdb
EDA课程设计\day1\DDS\PRJ\db\DDS.rtlv_sg.cdb
EDA课程设计\day1\DDS\PRJ\db\DDS.rtlv_sg_swap.cdb
EDA课程设计\day1\DDS\PRJ\db\DDS.sgate.rvd
EDA课程设计\day1\DDS\PRJ\db\DDS.sgate_sm.rvd
EDA课程设计\day1\DDS\PRJ\db\DDS.sgdiff.cdb
EDA课程设计\day1\DDS\PRJ\db\DDS.sgdiff.hdb
EDA课程设计\day1\DDS\PRJ\db\DDS.sld_design_entry.sci
EDA课程设计\day1\DDS\PRJ\db\DDS.sld_design_entry_dsc.sci
EDA课程设计\day1\DDS\PRJ\db\DDS.smart_action.txt
EDA课程设计\day1\DDS\PRJ\db\DDS.syn_hier_info
EDA课程设计\day1\DDS\PRJ\db\DDS.tis_db_list.ddb
EDA课程设计\day1\DDS\PRJ\db\DDS.tmw_info
EDA课程设计\day1\DDS\PRJ\db\logic_util_heursitic.dat
EDA课程设计\day1\DDS\PRJ\db\prev_cmp_DDS.qmsg
EDA课程设计\day1\DDS\PRJ\DDS.qpf
EDA课程设计\day1\DDS\PRJ\DDS.qsf
EDA课程设计\day1\DDS\PRJ\DDS.qws
EDA课程设计\day1\DDS\PRJ\ddsrom.mif
EDA课程设计\day1\DDS\PRJ\ddsrom.qip
EDA课程设计\day1\DDS\PRJ\ddsrom.v
EDA课程设计\day1\DDS\PRJ\ddsrom_bb.v
EDA课程设计\day1\DDS\PRJ\ddsrom_inst.v
EDA课程设计\day1\DDS\PRJ\DDS_nativelink_simulation.rpt
EDA课程设计\day1\DDS\PRJ\greybox_tmp\cbx_args.txt
EDA课程设计\day1\DDS\PRJ\incremental_db\compiled_partitions\DDS.db_info
EDA课程设计\day1\DDS\PRJ\incremental_db\compiled_partitions\DDS.root_partition.map.cdb
EDA课程设计\day1\DDS\PRJ\incremental_db\compiled_partitions\DDS.root_partition.map.dpi
EDA课程设计\day1\DDS\PRJ\incremental_db\compiled_partitions\DDS.root_partition.map.hbdb.cdb
EDA课程设计\day1\DDS\PRJ\incremental_db\compiled_partitions\DDS.root_partition.map.hbdb.hb_info
EDA课程设计\day1\DDS\PRJ\incremental_db\compiled_partitions\DDS.root_partition.map.hbdb.hdb
EDA课程设计\day1\DDS\PRJ\incremental_db\compiled_partitions\DDS.root_partition.map.hbdb.sig
EDA课程设计\day1\DDS\PRJ\incremental_db\compiled_partitions\DDS.root_partition.map.hdb
EDA课程设计\day1\DDS\PRJ\incremental_db\compiled_partitions\DDS.root_partition.map.kpt
EDA课程设计\day1\DDS\PRJ\incremental_db\README
EDA课程设计\day1\DDS\PRJ\output_files\DDS.done
EDA课程设计\day1\DDS\PRJ\output_files\DDS.flow.rpt
EDA课程设计\day1\DDS\PRJ\output_files\DDS.map.rpt
EDA课程设计\day1\DDS\PRJ\output_files\DDS.map.summary
EDA课程设计\day1\DDS\PRJ\simulation\modelsim\ddsrom.mif
EDA课程设计\day1\DDS\PRJ\simulation\modelsim\ddsrom.ver
EDA课程设计\day1\DDS\PRJ\simulation\modelsim\DDS_run_msim_rtl_verilog.do
EDA课程设计\day1\DDS\PRJ\simulation\modelsim\DDS_run_msim_rtl_verilog.do.bak
EDA课程设计\day1\DDS\PRJ\simulation\modelsim\DDS_run_msim_rtl_verilog.do.bak1
EDA课程设计\day1\DDS\PRJ\simulation\modelsim\DDS_run_msim_rtl_verilog.do.bak2
EDA课程设计\day1\DDS\PRJ\simulation\modelsim\DDS_run_msim_rtl_verilog.do.bak3
EDA课程设计\day1\DDS\PRJ\simulation\modelsim\DDS_run_msim_rtl_verilog.do.bak4
EDA课程设计\day1\DDS\PRJ\simulation\modelsim\modelsim.ini
EDA课程设计\day1\DDS\PRJ\simulation\modelsim\msim_transcript
EDA课程设计\day1\DDS\PRJ\simulation\modelsim\rtl_work\@d@d@s\verilog.prw
EDA课程设计\day1\DDS\PRJ\simulation\modelsim\rtl_work\@d@d@s\verilog.psm
EDA课程设计\day1\DDS\PRJ\simulation\modelsim\rtl_work\@d@d@s\_primary.dat
EDA课程设计\day1\DDS\PRJ\simulation\modelsim\rtl_work\@d@d@s\_primary.dbs
EDA课程设计\day1\DDS\PRJ\simulation\modelsim\rtl_work\@d@d@s\_primary.vhd
EDA课程设计\day1\DDS\PRJ\simulation\modelsim\rtl_work\@d@d@s_@module\verilog.prw
EDA课程设计\day1\DDS\PRJ\simulation\modelsim\rtl_work\@d@d@s_@module\verilog.psm
EDA课程设计\day1\DDS\PRJ\simulation\modelsim\rtl_work\@d@d@s_@module\_primary.dat
EDA课程设计\day1\DDS\PRJ\simulation\modelsim\rtl_work\@d@d@s_@module\_primary.dbs
EDA课程设计\day1\DDS\PRJ\simulation\modelsim\rtl_work\@d@d@s_@module\_primary.vhd
EDA课程设计\day1\DDS\PRJ\simulation\modelsim\rtl_work\@d@d@s_tb\verilog.prw
EDA课程设计\day1\DDS\PRJ\simulation\modelsim\rtl_work\@d@d@s_tb\verilog.psm
EDA课程设计\day1\DDS\PRJ\simulation\modelsim\rtl_work\@d@d@s_tb\_primary.dat
EDA课程设计\day1\DDS\PRJ\simulation\modelsim\rtl_work\@d@d@s_tb\_primary.dbs
EDA课程设计\day1\DDS\PRJ\simulation\modelsim\rtl_work\@d@d@s_tb\_primary.vhd
EDA课程设计\day1\DDS\PRJ\simulation\modelsim\rtl_work\ddsrom\verilog.prw
EDA课程设计\day1\DDS\PRJ\simulation\modelsim\rtl_work\ddsrom\verilog.psm
EDA课程设计\day1\DDS\PRJ\simulation\modelsim\rtl_work\ddsrom\_primary.dat
EDA课程设计\day1\DDS\PRJ\simulation\modelsim\rtl_work\ddsrom\_primary.dbs
EDA课程设计\day1\DDS\PRJ\simulation\modelsim\rtl_work\ddsrom\_primary.vhd
EDA课程设计\day1\DDS\PRJ\simulation\modelsim\rtl_work\_info
EDA课程设计\day1\DDS\PRJ\simulation\modelsim\rtl_work\_vmake
EDA课程设计\day1\DDS\PRJ\simulation\modelsim\vsim.wlf

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