Verilg to achieve frequency measurement and communication with STM32 in FSMC communication mode

fpga\db\.cmp.kpt
fpga\db\altsyncram_i124.tdf
fpga\db\altsyncram_m124.tdf
fpga\db\altsyncram_m504.tdf
fpga\db\cmpr_ngc.tdf
fpga\db\cmpr_rgc.tdf
fpga\db\cmpr_tgc.tdf
fpga\db\cntr_23j.tdf
fpga\db\cntr_egi.tdf
fpga\db\cntr_g9j.tdf
fpga\db\cntr_igi.tdf
fpga\db\cntr_o9j.tdf
fpga\db\cntr_pgi.tdf
fpga\db\decode_dvf.tdf
fpga\db\decode_rsa.tdf
fpga\db\icore3_adp.map_bb.logdb
fpga\db\icore3_adp_top.asm.qmsg
fpga\db\icore3_adp_top.asm.rdb
fpga\db\icore3_adp_top.asm_labs.ddb
fpga\db\icore3_adp_top.autoh_e40e1.map.reg_db.cdb
fpga\db\icore3_adp_top.autos_3e921.map.reg_db.cdb
fpga\db\icore3_adp_top.cbx.xml
fpga\db\icore3_adp_top.cmp.bpm
fpga\db\icore3_adp_top.cmp.cdb
fpga\db\icore3_adp_top.cmp.hdb
fpga\db\icore3_adp_top.cmp.idb
fpga\db\icore3_adp_top.cmp.logdb
fpga\db\icore3_adp_top.cmp.rdb
fpga\db\icore3_adp_top.cmp_merge.kpt
fpga\db\icore3_adp_top.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
fpga\db\icore3_adp_top.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
fpga\db\icore3_adp_top.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
fpga\db\icore3_adp_top.db_info
fpga\db\icore3_adp_top.eda.qmsg
fpga\db\icore3_adp_top.fit.qmsg
fpga\db\icore3_adp_top.hier_info
fpga\db\icore3_adp_top.hif
fpga\db\icore3_adp_top.ipinfo
fpga\db\icore3_adp_top.lpc.html
fpga\db\icore3_adp_top.lpc.rdb
fpga\db\icore3_adp_top.lpc.txt
fpga\db\icore3_adp_top.map.ammdb
fpga\db\icore3_adp_top.map.bpm
fpga\db\icore3_adp_top.map.cdb
fpga\db\icore3_adp_top.map.hdb
fpga\db\icore3_adp_top.map.kpt
fpga\db\icore3_adp_top.map.qmsg
fpga\db\icore3_adp_top.map.rdb
fpga\db\icore3_adp_top.map_bb.cdb
fpga\db\icore3_adp_top.map_bb.hdb
fpga\db\icore3_adp_top.npp.qmsg
fpga\db\icore3_adp_top.pplq.rdb
fpga\db\icore3_adp_top.pre_map.hdb
fpga\db\icore3_adp_top.pti_db_list.ddb
fpga\db\icore3_adp_top.root_partition.map.reg_db.cdb
fpga\db\icore3_adp_top.routing.rdb
fpga\db\icore3_adp_top.rtlv.hdb
fpga\db\icore3_adp_top.rtlv_sg.cdb
fpga\db\icore3_adp_top.rtlv_sg_swap.cdb
fpga\db\icore3_adp_top.sgate.nvd
fpga\db\icore3_adp_top.sgate_sm.nvd
fpga\db\icore3_adp_top.sgdiff.cdb
fpga\db\icore3_adp_top.sgdiff.hdb
fpga\db\icore3_adp_top.sld_design_entry.sci
fpga\db\icore3_adp_top.sld_design_entry_dsc.sci
fpga\db\icore3_adp_top.smart_action.txt
fpga\db\icore3_adp_top.sta.qmsg
fpga\db\icore3_adp_top.sta.rdb
fpga\db\icore3_adp_top.sta_cmp.8_slow_1200mv_85c.tdb
fpga\db\icore3_adp_top.tiscmp.fastest_slow_1200mv_0c.ddb
fpga\db\icore3_adp_top.tiscmp.fastest_slow_1200mv_85c.ddb
fpga\db\icore3_adp_top.tiscmp.fast_1200mv_0c.ddb
fpga\db\icore3_adp_top.tiscmp.slow_1200mv_0c.ddb
fpga\db\icore3_adp_top.tiscmp.slow_1200mv_85c.ddb
fpga\db\icore3_adp_top.tis_db_list.ddb
fpga\db\icore3_adp_top.vpr.ammdb
fpga\db\logic_util_heursitic.dat
fpga\db\mux_1pb.tdf
fpga\db\mux_rsc.tdf
fpga\db\mux_vsc.tdf
fpga\db\my_pll_altpll.v
fpga\db\prev_cmp_icore3_adp.qmsg
fpga\db\stp1_auto_stripped.stp
fpga\greybox_tmp\cbx_args.txt
fpga\icore3_adp.qpf
fpga\icore3_adp.tcl
fpga\icore3_adp.tcl.bak
fpga\icore3_adp_top.qsf
fpga\icore3_adp_top.qws
fpga\icore3_adp_top_nativelink_simulation.rpt
fpga\incremental_db\compiled_partitions\icore3_adp_top.autoh_e40e1.map.cdb
fpga\incremental_db\compiled_partitions\icore3_adp_top.autoh_e40e1.map.dpi
fpga\incremental_db\compiled_partitions\icore3_adp_top.autoh_e40e1.map.hdb
fpga\incremental_db\compiled_partitions\icore3_adp_top.autoh_e40e1.map.kpt
fpga\incremental_db\compiled_partitions\icore3_adp_top.autoh_e40e1.map.logdb
fpga\incremental_db\compiled_partitions\icore3_adp_top.autos_3e921.map.cdb
fpga\incremental_db\compiled_partitions\icore3_adp_top.autos_3e921.map.dpi
fpga\incremental_db\compiled_partitions\icore3_adp_top.autos_3e921.map.hdb
fpga\incremental_db\compiled_partitions\icore3_adp_top.autos_3e921.map.kpt
fpga\incremental_db\compiled_partitions\icore3_adp_top.autos_3e921.map.logdb

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