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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2017-07-31
  • Size : 226kb
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  • Author :nani****
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Introduction - If you have any usage issues, please Google them yourself
SPI verifcation in sv
Packet file list
(Preview for download)
spi_vip\docs
spi_vip\docs\spi_vip_user_manual.pdf
spi_vip\examples
spi_vip\examples\sim
spi_vip\examples\sim\file_list.f
spi_vip\examples\testbench
spi_vip\examples\testbench\packet.sv
spi_vip\examples\testbench\test.sv
spi_vip\examples\testbench\testbench_top.sv
spi_vip\verification_ip
spi_vip\verification_ip\master
spi_vip\verification_ip\master\spi_m.sv
spi_vip\verification_ip\master\spi_m_if.sv
spi_vip\verification_ip\slave
spi_vip\verification_ip\slave\spi_s.sv
spi_vip\verification_ip\slave\spi_s_if.sv
spi_vip
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