Accurate realization of odd frequency division, the FPGA development board provides 25MHZ clock frequency divided into 1MHZ, containing test files

encoder_clk
encoder_clk\encoder_clk
encoder_clk\encoder_clk\code
encoder_clk\encoder_clk\code\test.v
encoder_clk\encoder_clk\code\test_clk.v
encoder_clk\encoder_clk\code\yinjian.ucf
encoder_clk\encoder_clk\encoder_clk.gise
encoder_clk\encoder_clk\encoder_clk.xise
encoder_clk\encoder_clk\fuse.log
encoder_clk\encoder_clk\fuse.xmsgs
encoder_clk\encoder_clk\fuseRelaunch.cmd
encoder_clk\encoder_clk\ipcore_dir
encoder_clk\encoder_clk\iseconfig
encoder_clk\encoder_clk\iseconfig\encoder_clk.projectmgr
encoder_clk\encoder_clk\iseconfig\test_clk.xreport
encoder_clk\encoder_clk\isim
encoder_clk\encoder_clk\isim.cmd
encoder_clk\encoder_clk\isim.log
encoder_clk\encoder_clk\isim\isim_usage_statistics.html
encoder_clk\encoder_clk\isim\pn_info
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\isimcrash.log
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\ISimEngine-DesignHierarchy.dbg
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\isimkernel.log
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\libPortability.dll
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\netId.dat
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\test_isim_beh.exe
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\tmp_save
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\tmp_save\_1
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\work
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\work\m_00000000000867157637_1985558087.c
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\work\m_00000000000867157637_1985558087.didat
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\work\m_00000000000867157637_1985558087.nt64.obj
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\work\m_00000000002145102365_1765943307.c
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\work\m_00000000002145102365_1765943307.didat
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\work\m_00000000002145102365_1765943307.nt64.obj
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\work\m_00000000004134447467_2073120511.c
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\work\m_00000000004134447467_2073120511.didat
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\work\m_00000000004134447467_2073120511.nt64.obj
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\work\test_isim_beh.exe_main.c
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\work\test_isim_beh.exe_main.nt64.obj
encoder_clk\encoder_clk\isim\work
encoder_clk\encoder_clk\isim\work\glbl.sdb
encoder_clk\encoder_clk\isim\work\test.sdb
encoder_clk\encoder_clk\isim\work\test_clk.sdb
encoder_clk\encoder_clk\test_beh.prj
encoder_clk\encoder_clk\test_clk.bgn
encoder_clk\encoder_clk\test_clk.bit
encoder_clk\encoder_clk\test_clk.bld
encoder_clk\encoder_clk\test_clk.cmd_log
encoder_clk\encoder_clk\test_clk.drc
encoder_clk\encoder_clk\test_clk.lso
encoder_clk\encoder_clk\test_clk.ncd
encoder_clk\encoder_clk\test_clk.ngc
encoder_clk\encoder_clk\test_clk.ngd
encoder_clk\encoder_clk\test_clk.ngr
encoder_clk\encoder_clk\test_clk.pad
encoder_clk\encoder_clk\test_clk.par
encoder_clk\encoder_clk\test_clk.pcf
encoder_clk\encoder_clk\test_clk.prj
encoder_clk\encoder_clk\test_clk.ptwx
encoder_clk\encoder_clk\test_clk.stx
encoder_clk\encoder_clk\test_clk.syr
encoder_clk\encoder_clk\test_clk.twr
encoder_clk\encoder_clk\test_clk.twx
encoder_clk\encoder_clk\test_clk.unroutes
encoder_clk\encoder_clk\test_clk.ut
encoder_clk\encoder_clk\test_clk.xpi
encoder_clk\encoder_clk\test_clk.xst
encoder_clk\encoder_clk\test_clk_bitgen.xwbt
encoder_clk\encoder_clk\test_clk_envsettings.html
encoder_clk\encoder_clk\test_clk_guide.ncd
encoder_clk\encoder_clk\test_clk_map.map
encoder_clk\encoder_clk\test_clk_map.mrp
encoder_clk\encoder_clk\test_clk_map.ncd
encoder_clk\encoder_clk\test_clk_map.ngm
encoder_clk\encoder_clk\test_clk_map.xrpt
encoder_clk\encoder_clk\test_clk_ngdbuild.xrpt
encoder_clk\encoder_clk\test_clk_pad.csv
encoder_clk\encoder_clk\test_clk_pad.txt
encoder_clk\encoder_clk\test_clk_par.xrpt
encoder_clk\encoder_clk\test_clk_summary.html
encoder_clk\encoder_clk\test_clk_summary.xml
encoder_clk\encoder_clk\test_clk_usage.xml
encoder_clk\encoder_clk\test_clk_xst.xrpt
encoder_clk\encoder_clk\test_isim_beh.exe
encoder_clk\encoder_clk\test_isim_beh.wdb
encoder_clk\encoder_clk\usage_statistics_webtalk.html
encoder_clk\encoder_clk\webtalk.log
encoder_clk\encoder_clk\webtalk_pn.xml
encoder_clk\encoder_clk\xilinxsim.ini
encoder_clk\encoder_clk\xlnx_auto_0_xdb
encoder_clk\encoder_clk\xlnx_auto_0_xdb\cst.xbcd
encoder_clk\encoder_clk\xst
encoder_clk\encoder_clk\xst\dump.xst
encoder_clk\encoder_clk\xst\dump.xst\test_clk.prj
encoder_clk\encoder_clk\xst\dump.xst\test_clk.prj\ngx
encoder_clk\encoder_clk\xst\dump.xst\test_clk.prj\ngx\notopt
encoder_clk\encoder_clk\xst\dump.xst\test_clk.prj\ngx\opt
encoder_clk\encoder_clk\xst\projnav.tmp

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