Use Verilog programming to build the test platform, and connect the VGA and other peripherals, using MIPS assembly to write logic to complete the dodge ball game

_ngo
_ngo\netlist.lst
_xmsgs
_xmsgs\bitgen.xmsgs
_xmsgs\map.xmsgs
_xmsgs\ngdbuild.xmsgs
_xmsgs\par.xmsgs
_xmsgs\pn_parser.xmsgs
_xmsgs\trce.xmsgs
_xmsgs\xst.xmsgs
add_32.v
ALU_v.v
clk_div.sym
clk_div.v
Counter.ngc
Counter.sym
Counter_3_IO.v
Display.ngc
Display.sym
Display.v
Display_IO.v
Display_summary.html
Ext_32.v
fuse.log
fuse.xmsgs
fuseRelaunch.cmd
GPIO.ngc
GPIO.sym
GPIO.v
GPIO_IO.v
HexTo8SEG.sym
HexTo8SEG.v
HexTo8SEG_summary.html
ipcore_dir
ipcore_dir\_xmsgs
ipcore_dir\_xmsgs\cg.xmsgs
ipcore_dir\_xmsgs\pn_parser.xmsgs
ipcore_dir\blk_mem_gen_v7_3.asy
ipcore_dir\blk_mem_gen_v7_3.gise
ipcore_dir\blk_mem_gen_v7_3.mif
ipcore_dir\blk_mem_gen_v7_3.ngc
ipcore_dir\blk_mem_gen_v7_3.sym
ipcore_dir\blk_mem_gen_v7_3.v
ipcore_dir\blk_mem_gen_v7_3.veo
ipcore_dir\blk_mem_gen_v7_3.xco
ipcore_dir\blk_mem_gen_v7_3.xise
ipcore_dir\blk_mem_gen_v7_3
ipcore_dir\blk_mem_gen_v7_3\blk_mem_gen_v7_3_readme.txt
ipcore_dir\blk_mem_gen_v7_3\doc
ipcore_dir\blk_mem_gen_v7_3\doc\blk_mem_gen_v7_3_vinfo.html
ipcore_dir\blk_mem_gen_v7_3\example_design
ipcore_dir\blk_mem_gen_v7_3\example_design\blk_mem_gen_v7_3_exdes.ucf
ipcore_dir\blk_mem_gen_v7_3\example_design\blk_mem_gen_v7_3_exdes.vhd
ipcore_dir\blk_mem_gen_v7_3\example_design\blk_mem_gen_v7_3_exdes.xdc
ipcore_dir\blk_mem_gen_v7_3\example_design\blk_mem_gen_v7_3_prod.vhd
ipcore_dir\blk_mem_gen_v7_3\implement
ipcore_dir\blk_mem_gen_v7_3\implement\implement.bat
ipcore_dir\blk_mem_gen_v7_3\implement\implement.sh
ipcore_dir\blk_mem_gen_v7_3\implement\planAhead_ise.bat
ipcore_dir\blk_mem_gen_v7_3\implement\planAhead_ise.sh
ipcore_dir\blk_mem_gen_v7_3\implement\planAhead_ise.tcl
ipcore_dir\blk_mem_gen_v7_3\implement\xst.prj
ipcore_dir\blk_mem_gen_v7_3\implement\xst.scr
ipcore_dir\blk_mem_gen_v7_3\simulation
ipcore_dir\blk_mem_gen_v7_3\simulation\addr_gen.vhd
ipcore_dir\blk_mem_gen_v7_3\simulation\blk_mem_gen_v7_3_synth.vhd
ipcore_dir\blk_mem_gen_v7_3\simulation\blk_mem_gen_v7_3_tb.vhd
ipcore_dir\blk_mem_gen_v7_3\simulation\bmg_stim_gen.vhd
ipcore_dir\blk_mem_gen_v7_3\simulation\bmg_tb_pkg.vhd
ipcore_dir\blk_mem_gen_v7_3\simulation\checker.vhd
ipcore_dir\blk_mem_gen_v7_3\simulation\data_gen.vhd
ipcore_dir\blk_mem_gen_v7_3\simulation\functional
ipcore_dir\blk_mem_gen_v7_3\simulation\functional\simcmds.tcl
ipcore_dir\blk_mem_gen_v7_3\simulation\functional\simulate_isim.bat
ipcore_dir\blk_mem_gen_v7_3\simulation\functional\simulate_mti.bat
ipcore_dir\blk_mem_gen_v7_3\simulation\functional\simulate_mti.do
ipcore_dir\blk_mem_gen_v7_3\simulation\functional\simulate_mti.sh
ipcore_dir\blk_mem_gen_v7_3\simulation\functional\simulate_ncsim.sh
ipcore_dir\blk_mem_gen_v7_3\simulation\functional\simulate_vcs.sh
ipcore_dir\blk_mem_gen_v7_3\simulation\functional\ucli_commands.key
ipcore_dir\blk_mem_gen_v7_3\simulation\functional\vcs_session.tcl
ipcore_dir\blk_mem_gen_v7_3\simulation\functional\wave_mti.do
ipcore_dir\blk_mem_gen_v7_3\simulation\functional\wave_ncsim.sv
ipcore_dir\blk_mem_gen_v7_3\simulation\random.vhd
ipcore_dir\blk_mem_gen_v7_3\simulation\timing
ipcore_dir\blk_mem_gen_v7_3\simulation\timing\simcmds.tcl
ipcore_dir\blk_mem_gen_v7_3\simulation\timing\simulate_isim.bat
ipcore_dir\blk_mem_gen_v7_3\simulation\timing\simulate_mti.bat
ipcore_dir\blk_mem_gen_v7_3\simulation\timing\simulate_mti.do
ipcore_dir\blk_mem_gen_v7_3\simulation\timing\simulate_mti.sh
ipcore_dir\blk_mem_gen_v7_3\simulation\timing\simulate_ncsim.sh
ipcore_dir\blk_mem_gen_v7_3\simulation\timing\simulate_vcs.sh
ipcore_dir\blk_mem_gen_v7_3\simulation\timing\ucli_commands.key
ipcore_dir\blk_mem_gen_v7_3\simulation\timing\vcs_session.tcl
ipcore_dir\blk_mem_gen_v7_3\simulation\timing\wave_mti.do
ipcore_dir\blk_mem_gen_v7_3\simulation\timing\wave_ncsim.sv
ipcore_dir\blk_mem_gen_v7_3_flist.txt
ipcore_dir\blk_mem_gen_v7_3_xmdf.tcl
ipcore_dir\coregen.cgp
ipcore_dir\coregen.log

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