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27_adda_test
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VHDL-FPGA-Verilog
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Update : 2017-08-04
Size : 5.7mb
Downloaded :0次
Author :
安*****
About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
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The ADDA module code applies to the black gold FPGA development board, the 35M sampling rate
Packet file list
(Preview for download)
27_adda_test
27_adda_test\_ngo
27_adda_test\_ngo\netlist.lst
27_adda_test\_xmsgs
27_adda_test\_xmsgs\bitgen.xmsgs
27_adda_test\_xmsgs\map.xmsgs
27_adda_test\_xmsgs\ngdbuild.xmsgs
27_adda_test\_xmsgs\par.xmsgs
27_adda_test\_xmsgs\pn_parser.xmsgs
27_adda_test\_xmsgs\trce.xmsgs
27_adda_test\_xmsgs\xst.xmsgs
27_adda_test\adda.cpj
27_adda_test\adda_test.bgn
27_adda_test\adda_test.bit
27_adda_test\adda_test.bld
27_adda_test\adda_test.cmd_log
27_adda_test\adda_test.drc
27_adda_test\adda_test.gise
27_adda_test\adda_test.lso
27_adda_test\adda_test.ncd
27_adda_test\adda_test.ngc
27_adda_test\adda_test.ngd
27_adda_test\adda_test.ngr
27_adda_test\adda_test.pad
27_adda_test\adda_test.par
27_adda_test\adda_test.pcf
27_adda_test\adda_test.prj
27_adda_test\adda_test.ptwx
27_adda_test\adda_test.stx
27_adda_test\adda_test.syr
27_adda_test\adda_test.twr
27_adda_test\adda_test.twx
27_adda_test\adda_test.ucf
27_adda_test\adda_test.unroutes
27_adda_test\adda_test.ut
27_adda_test\adda_test.v
27_adda_test\adda_test.xise
27_adda_test\adda_test.xpi
27_adda_test\adda_test.xst
27_adda_test\adda_test_bitgen.xwbt
27_adda_test\adda_test_envsettings.html
27_adda_test\adda_test_guide.ncd
27_adda_test\adda_test_map.map
27_adda_test\adda_test_map.mrp
27_adda_test\adda_test_map.ncd
27_adda_test\adda_test_map.ngm
27_adda_test\adda_test_map.xrpt
27_adda_test\adda_test_ngdbuild.xrpt
27_adda_test\adda_test_pad.csv
27_adda_test\adda_test_pad.txt
27_adda_test\adda_test_par.xrpt
27_adda_test\adda_test_summary.html
27_adda_test\adda_test_summary.xml
27_adda_test\adda_test_usage.xml
27_adda_test\adda_test_xst.xrpt
27_adda_test\chipscope_icon.ngc
27_adda_test\chipscope_icon.v
27_adda_test\chipscope_ila.ngc
27_adda_test\chipscope_ila.v
27_adda_test\ipcore_dir
27_adda_test\ipcore_dir\.lso
27_adda_test\ipcore_dir\FIR.asy
27_adda_test\ipcore_dir\FIR.gise
27_adda_test\ipcore_dir\FIR.mif
27_adda_test\ipcore_dir\FIR.ncf
27_adda_test\ipcore_dir\FIR.ngc
27_adda_test\ipcore_dir\FIR.sym
27_adda_test\ipcore_dir\FIR.v
27_adda_test\ipcore_dir\FIR.veo
27_adda_test\ipcore_dir\FIR.xco
27_adda_test\ipcore_dir\FIR.xise
27_adda_test\ipcore_dir\FIRCOEFF_auto0_0.mif
27_adda_test\ipcore_dir\FIRCOEFF_auto0_1.mif
27_adda_test\ipcore_dir\FIRCOEFF_auto0_2.mif
27_adda_test\ipcore_dir\FIRCOEFF_auto0_3.mif
27_adda_test\ipcore_dir\FIRCOEFF_auto0_4.mif
27_adda_test\ipcore_dir\FIRCOEFF_auto0_5.mif
27_adda_test\ipcore_dir\FIRCOEFF_auto0_6.mif
27_adda_test\ipcore_dir\FIR_flist.txt
27_adda_test\ipcore_dir\FIR_readme.txt
27_adda_test\ipcore_dir\FIR_xmdf.tcl
27_adda_test\ipcore_dir\FIRfilt_decode_rom.mif
27_adda_test\ipcore_dir\PLL
27_adda_test\ipcore_dir\PLL\clk_wiz_v3_6_readme.txt
27_adda_test\ipcore_dir\PLL\doc
27_adda_test\ipcore_dir\PLL\doc\clk_wiz_v3_6_readme.txt
27_adda_test\ipcore_dir\PLL\doc\clk_wiz_v3_6_vinfo.html
27_adda_test\ipcore_dir\PLL\doc\pg065_clk_wiz.pdf
27_adda_test\ipcore_dir\PLL\example_design
27_adda_test\ipcore_dir\PLL\example_design\PLL_exdes.ucf
27_adda_test\ipcore_dir\PLL\example_design\PLL_exdes.v
27_adda_test\ipcore_dir\PLL\example_design\PLL_exdes.xdc
27_adda_test\ipcore_dir\PLL\implement
27_adda_test\ipcore_dir\PLL\implement\implement.bat
27_adda_test\ipcore_dir\PLL\implement\implement.sh
27_adda_test\ipcore_dir\PLL\implement\planAhead_ise.bat
27_adda_test\ipcore_dir\PLL\implement\planAhead_ise.sh
27_adda_test\ipcore_dir\PLL\implement\planAhead_ise.tcl
27_adda_test\ipcore_dir\PLL\implement\planAhead_rdn.bat
27_adda_test\ipcore_dir\PLL\implement\planAhead_rdn.sh
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