Design of DDS based on FPGA

DDS\Block1.bdf
DDS\cmp_state.ini
DDS\db\altsyncram_joq.tdf
DDS\db\altsyncram_soq.tdf
DDS\db\DDS.db_info
DDS\db\DDS.eco.cdb
DDS\db\DDS.sim.vwf
DDS\db\DDS.sld_design_entry.sci
DDS\db\DDS_cmp.qrpt
DDS\db\DDS_sim.qrpt
DDS\DDS.asm.rpt
DDS\DDS.bsf
DDS\DDS.done
DDS\DDS.fit.eqn
DDS\DDS.fit.rpt
DDS\DDS.fit.summary
DDS\DDS.flow.rpt
DDS\DDS.map.eqn
DDS\DDS.map.rpt
DDS\DDS.map.summary
DDS\DDS.pin
DDS\DDS.pof
DDS\DDS.qpf
DDS\DDS.qsf
DDS\DDS.qws
DDS\DDS.sim.rpt
DDS\DDS.sof
DDS\DDS.tan.rpt
DDS\DDS.tan.summary
DDS\DDS.vhd
DDS\DDS.vwf
DDS\DDS_assignment_defaults.qdf
DDS\SIN_ROM.bsf
DDS\SIN_ROM.hex
DDS\SIN_ROM.inc
DDS\SIN_ROM.vhd
DDS\db
DDS

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