This is a four bit sequence detector, including three modes that can be selected: increment mode (detecting four consistency increment data), decrement mode (detecting four consistency decrement data) and steadiness mode (detecting four consistency same data). The whole design adopts synchronous clock, asynchronous reset, and uses Mealy state machine. The whole file concludes the simulation environment and testbench.

SEQ_DETECTOR\rtl\SEQ_DETECTOR.v
SEQ_DETECTOR\sim\cm.log
SEQ_DETECTOR\sim\csrc\amcQwB.o
SEQ_DETECTOR\sim\csrc\archive.43\_19525_archive_1.a
SEQ_DETECTOR\sim\csrc\archive.43\_19525_archive_1.a.info
SEQ_DETECTOR\sim\csrc\cginfo.json
SEQ_DETECTOR\sim\csrc\cgproc.19525.json
SEQ_DETECTOR\sim\csrc\filelist
SEQ_DETECTOR\sim\csrc\filelist.cu
SEQ_DETECTOR\sim\csrc\filelist.dpi
SEQ_DETECTOR\sim\csrc\filelist.hsopt
SEQ_DETECTOR\sim\csrc\filelist.hsopt.llvm2_0.objs
SEQ_DETECTOR\sim\csrc\filelist.hsopt.objs
SEQ_DETECTOR\sim\csrc\filelist.pli
SEQ_DETECTOR\sim\csrc\import_dpic.h
SEQ_DETECTOR\sim\csrc\incr.sdb
SEQ_DETECTOR\sim\csrc\Makefile
SEQ_DETECTOR\sim\csrc\Makefile.hsopt
SEQ_DETECTOR\sim\csrc\objs\amcQw_d.o
SEQ_DETECTOR\sim\csrc\product_timestamp
SEQ_DETECTOR\sim\csrc\rmapats.c
SEQ_DETECTOR\sim\csrc\rmapats.h
SEQ_DETECTOR\sim\csrc\rmapats.m
SEQ_DETECTOR\sim\csrc\rmapats.o
SEQ_DETECTOR\sim\csrc\rmapats_mop.o
SEQ_DETECTOR\sim\csrc\rmar.c
SEQ_DETECTOR\sim\csrc\rmar.h
SEQ_DETECTOR\sim\csrc\rmar.o
SEQ_DETECTOR\sim\csrc\rmar0.h
SEQ_DETECTOR\sim\csrc\rmar_llvm_0_0.o
SEQ_DETECTOR\sim\csrc\rmar_llvm_0_1.o
SEQ_DETECTOR\sim\csrc\SIM_l.o
SEQ_DETECTOR\sim\csrc\vcspieces.incr
SEQ_DETECTOR\sim\csrc\_10399_archive_1.so
SEQ_DETECTOR\sim\csrc\_10527_archive_1.so
SEQ_DETECTOR\sim\csrc\_10960_archive_1.so
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SEQ_DETECTOR\sim\csrc\_12946_archive_1.so
SEQ_DETECTOR\sim\csrc\_12978_archive_1.so
SEQ_DETECTOR\sim\csrc\_14656_archive_1.so
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SEQ_DETECTOR\sim\csrc\_1890_archive_1.so
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SEQ_DETECTOR\sim\csrc\_20654_archive_1.so
SEQ_DETECTOR\sim\csrc\_20665_archive_1.so
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SEQ_DETECTOR\sim\csrc\_2404_archive_1.so
SEQ_DETECTOR\sim\csrc\_26882_archive_1.so
SEQ_DETECTOR\sim\csrc\_27534_archive_1.so
SEQ_DETECTOR\sim\csrc\_27933_archive_1.so
SEQ_DETECTOR\sim\csrc\_28353_archive_1.so
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SEQ_DETECTOR\sim\csrc\_31820_archive_1.so
SEQ_DETECTOR\sim\csrc\_31908_archive_1.so
SEQ_DETECTOR\sim\csrc\_32592_archive_1.so
SEQ_DETECTOR\sim\csrc\_3326_archive_1.so
SEQ_DETECTOR\sim\csrc\_5506_archive_1.so
SEQ_DETECTOR\sim\csrc\_5648_archive_1.so
SEQ_DETECTOR\sim\csrc\_5998_archive_1.so
SEQ_DETECTOR\sim\csrc\_8104_archive_1.so
SEQ_DETECTOR\sim\csrc\_9465_archive_1.so
SEQ_DETECTOR\sim\csrc\_9587_archive_1.so
SEQ_DETECTOR\sim\csrc\_prev_archive_1.so
SEQ_DETECTOR\sim\csrc\_prev_cginfo.json
SEQ_DETECTOR\sim\csrc\_vcs_const_SIM_0.incr.dat
SEQ_DETECTOR\sim\csrc\_vcs_etype_SIM_0.incr.dat
SEQ_DETECTOR\sim\csrc\_vcs_pli_stub_.c
SEQ_DETECTOR\sim\csrc\_vcs_pli_stub_.o
SEQ_DETECTOR\sim\makefile
SEQ_DETECTOR\sim\novas.conf
SEQ_DETECTOR\sim\novas.rc
SEQ_DETECTOR\sim\novas_dump.log
SEQ_DETECTOR\sim\simfiles.f
SEQ_DETECTOR\sim\simv
SEQ_DETECTOR\sim\simv.daidir\.vcs.timestamp.tmp
SEQ_DETECTOR\sim\simv.daidir\binmap.sdb
SEQ_DETECTOR\sim\simv.daidir\build_db
SEQ_DETECTOR\sim\simv.daidir\cc\cc_bcode.db
SEQ_DETECTOR\sim\simv.daidir\cc\cc_dummy_file
SEQ_DETECTOR\sim\simv.daidir\cgname.json
SEQ_DETECTOR\sim\simv.daidir\covg_defs
SEQ_DETECTOR\sim\simv.daidir\debug_dump\.version
SEQ_DETECTOR\sim\simv.daidir\debug_dump\dumpcheck.db
SEQ_DETECTOR\sim\simv.daidir\debug_dump\HsimSigOptDb.sdb
SEQ_DETECTOR\sim\simv.daidir\debug_dump\src_files_verilog
SEQ_DETECTOR\sim\simv.daidir\debug_dump\topmodules

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