Using Verilog to achieve RTLAB multi-channel driver

FPGA_program\.Xil-PlanAhead-5556-7KOPJF1P4RLZLRN\ngc2edif\ngc2edif.log
FPGA_program\.Xil-PlanAhead-5556-7KOPJF1P4RLZLRN\ngc2edif\RTLAB.edif
FPGA_program\.Xil-PlanAhead-5556-7KOPJF1P4RLZLRN\ngc2edif\_xmsgs\ngc2edif.xmsgs
FPGA_program\7.cfi
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FPGA_program\clkdiv.prj
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FPGA_program\ipcore_dir\sinrom_xmdf.tcl
FPGA_program\ipcore_dir\sjrom.asy
FPGA_program\ipcore_dir\sjrom.gise
FPGA_program\ipcore_dir\sjrom.ise
FPGA_program\ipcore_dir\sjrom.mif
FPGA_program\ipcore_dir\sjrom.ncf
FPGA_program\ipcore_dir\sjrom.ngc
FPGA_program\ipcore_dir\sjrom.sym
FPGA_program\ipcore_dir\sjrom.v
FPGA_program\ipcore_dir\sjrom.veo
FPGA_program\ipcore_dir\sjrom.vhd
FPGA_program\ipcore_dir\sjrom.vho
FPGA_program\ipcore_dir\sjrom.xco
FPGA_program\ipcore_dir\sjrom.xise

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