Use Verilog implementation of global asynchronous receive transmitter in quartus platform test successfully

UART\db\logic_util_heursitic.dat
UART\db\prev_cmp_uart.qmsg
UART\db\uart.amm.cdb
UART\db\uart.asm.qmsg
UART\db\uart.asm.rdb
UART\db\uart.asm_labs.ddb
UART\db\uart.cbx.xml
UART\db\uart.cmp.cdb
UART\db\uart.cmp.hdb
UART\db\uart.cmp.kpt
UART\db\uart.cmp.logdb
UART\db\uart.cmp.rdb
UART\db\uart.cmp0.ddb
UART\db\uart.db_info
UART\db\uart.fit.qmsg
UART\db\uart.hier_info
UART\db\uart.hif
UART\db\uart.idb.cdb
UART\db\uart.lpc.html
UART\db\uart.lpc.rdb
UART\db\uart.lpc.txt
UART\db\uart.map.cdb
UART\db\uart.map.hdb
UART\db\uart.map.logdb
UART\db\uart.map.qmsg
UART\db\uart.pre_map.cdb
UART\db\uart.pre_map.hdb
UART\db\uart.rtlv.hdb
UART\db\uart.rtlv_sg.cdb
UART\db\uart.rtlv_sg_swap.cdb
UART\db\uart.sgdiff.cdb
UART\db\uart.sgdiff.hdb
UART\db\uart.sld_design_entry.sci
UART\db\uart.sld_design_entry_dsc.sci
UART\db\uart.smart_action.txt
UART\db\uart.sta.qmsg
UART\db\uart.sta.rdb
UART\db\uart.sta_cmp.5_slow.tdb
UART\db\uart.syn_hier_info
UART\db\uart.tis_db_list.ddb
UART\db\uart.tmw_info
UART\incremental_db\compiled_partitions\uart.db_info
UART\incremental_db\compiled_partitions\uart.root_partition.map.kpt
UART\incremental_db\README
UART\uart.asm.rpt
UART\uart.cdf
UART\uart.done
UART\uart.fit.rpt
UART\uart.fit.smsg
UART\uart.fit.summary
UART\uart.flow.rpt
UART\uart.map.rpt
UART\uart.map.summary
UART\uart.pin
UART\uart.pof
UART\uart.qpf
UART\uart.qsf
UART\uart.sta.rpt
UART\uart.sta.summary
UART\uart.v
UART\uart_assignment_defaults.qdf
UART\Verilog2.v
UART\Verilog3.v
UART\Verilog4.v
UART\incremental_db\compiled_partitions
UART\db
UART\incremental_db
UART

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