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ram_2
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Category :
VHDL-FPGA-Verilog
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Update : 2017-08-10
Size : 10.88mb
Downloaded :0次
Author :
么么哒哈****
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Introduction - If you have any usage issues, please Google them yourself
Reedit
Dual port RAM, readable and writable, written in Verilog. Hope to communicate with great God, ask God to correct me
Packet file list
(Preview for download)
ram_2\.qsys_edit\filters.xml
ram_2\.qsys_edit\preferences.xml
ram_2\.qsys_edit\test.xml
ram_2\.qsys_edit\test_ram.xml
ram_2\.qsys_edit\test_ram_schematic.nlv
ram_2\.qsys_edit\test_schematic.nlv
ram_2\.qsys_edit\unsaved.xml
ram_2\.qsys_edit\unsaved_schematic.nlv
ram_2\c5_pin_model_dump.txt
ram_2\db\.cmp.kpt
ram_2\db\altsyncram_ncj2.tdf
ram_2\db\prev_cmp_test_ram.qmsg
ram_2\db\test_ram.ae.hdb
ram_2\db\test_ram.asm.qmsg
ram_2\db\test_ram.asm.rdb
ram_2\db\test_ram.cbx.xml
ram_2\db\test_ram.cmp.bpm
ram_2\db\test_ram.cmp.cdb
ram_2\db\test_ram.cmp.hdb
ram_2\db\test_ram.cmp.idb
ram_2\db\test_ram.cmp.logdb
ram_2\db\test_ram.cmp.rdb
ram_2\db\test_ram.cmp_merge.kpt
ram_2\db\test_ram.cyclonev_io_sim_cache.ff_100c_fast.hsd
ram_2\db\test_ram.cyclonev_io_sim_cache.ff_n40c_fast.hsd
ram_2\db\test_ram.cyclonev_io_sim_cache.ii_100c_slow.hsd
ram_2\db\test_ram.cyclonev_io_sim_cache.ii_85c_slow.hsd
ram_2\db\test_ram.cyclonev_io_sim_cache.ii_n40c_slow.hsd
ram_2\db\test_ram.db_info
ram_2\db\test_ram.eda.qmsg
ram_2\db\test_ram.fit.qmsg
ram_2\db\test_ram.hier_info
ram_2\db\test_ram.hif
ram_2\db\test_ram.lpc.html
ram_2\db\test_ram.lpc.rdb
ram_2\db\test_ram.lpc.txt
ram_2\db\test_ram.map.ammdb
ram_2\db\test_ram.map.bpm
ram_2\db\test_ram.map.cdb
ram_2\db\test_ram.map.hdb
ram_2\db\test_ram.map.kpt
ram_2\db\test_ram.map.logdb
ram_2\db\test_ram.map.qmsg
ram_2\db\test_ram.map.rdb
ram_2\db\test_ram.map_bb.cdb
ram_2\db\test_ram.map_bb.hdb
ram_2\db\test_ram.map_bb.logdb
ram_2\db\test_ram.pplq.rdb
ram_2\db\test_ram.pre_map.cdb
ram_2\db\test_ram.pre_map.hdb
ram_2\db\test_ram.root_partition.map.reg_db.cdb
ram_2\db\test_ram.routing.rdb
ram_2\db\test_ram.rtlv.hdb
ram_2\db\test_ram.rtlv_sg.cdb
ram_2\db\test_ram.rtlv_sg_swap.cdb
ram_2\db\test_ram.sld_design_entry.sci
ram_2\db\test_ram.sld_design_entry_dsc.sci
ram_2\db\test_ram.smart_action.txt
ram_2\db\test_ram.sta.qmsg
ram_2\db\test_ram.sta.rdb
ram_2\db\test_ram.tiscmp.fastest_slow_1100mv_85c.ddb
ram_2\db\test_ram.tiscmp.fastest_slow_1100mv_n40c.ddb
ram_2\db\test_ram.tiscmp.fast_1100mv_100c.ddb
ram_2\db\test_ram.tiscmp.fast_1100mv_n40c.ddb
ram_2\db\test_ram.tiscmp.slow_1100mv_100c.ddb
ram_2\db\test_ram.tiscmp.slow_1100mv_n40c.ddb
ram_2\db\test_ram.tis_db_list.ddb
ram_2\db\test_ram.vpr.ammdb
ram_2\db\test_ram_partition_pins.json
ram_2\greybox_tmp\cbx_args.txt
ram_2\incremental_db\compiled_partitions\test_ram.db_info
ram_2\incremental_db\compiled_partitions\test_ram.root_partition.cmp.ammdb
ram_2\incremental_db\compiled_partitions\test_ram.root_partition.cmp.cdb
ram_2\incremental_db\compiled_partitions\test_ram.root_partition.cmp.dfp
ram_2\incremental_db\compiled_partitions\test_ram.root_partition.cmp.hbdb.cdb
ram_2\incremental_db\compiled_partitions\test_ram.root_partition.cmp.hbdb.hdb
ram_2\incremental_db\compiled_partitions\test_ram.root_partition.cmp.hbdb.sig
ram_2\incremental_db\compiled_partitions\test_ram.root_partition.cmp.hdb
ram_2\incremental_db\compiled_partitions\test_ram.root_partition.cmp.logdb
ram_2\incremental_db\compiled_partitions\test_ram.root_partition.cmp.rcfdb
ram_2\incremental_db\compiled_partitions\test_ram.root_partition.map.cdb
ram_2\incremental_db\compiled_partitions\test_ram.root_partition.map.dpi
ram_2\incremental_db\compiled_partitions\test_ram.root_partition.map.hbdb.cdb
ram_2\incremental_db\compiled_partitions\test_ram.root_partition.map.hbdb.hb_info
ram_2\incremental_db\compiled_partitions\test_ram.root_partition.map.hbdb.hdb
ram_2\incremental_db\compiled_partitions\test_ram.root_partition.map.hbdb.sig
ram_2\incremental_db\compiled_partitions\test_ram.root_partition.map.hdb
ram_2\incremental_db\compiled_partitions\test_ram.root_partition.map.kpt
ram_2\incremental_db\compiled_partitions\test_ram.rrp.hdb
ram_2\incremental_db\compiled_partitions\test_ram.rrs.cdb
ram_2\incremental_db\README
ram_2\output_files\test_ram.asm.rpt
ram_2\output_files\test_ram.done
ram_2\output_files\test_ram.eda.rpt
ram_2\output_files\test_ram.fit.rpt
ram_2\output_files\test_ram.fit.smsg
ram_2\output_files\test_ram.fit.summary
ram_2\output_files\test_ram.flow.rpt
ram_2\output_files\test_ram.jdi
ram_2\output_files\test_ram.map.rpt
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