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dengjingdu

  • Category : VHDL-FPGA-Verilog
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  • Update : 2017-08-10
  • Size : 38.42mb
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  • Author :dasds*****
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Introduction - If you have any usage issues, please Google them yourself
The accuracy of measurement, the higher the frequency accuracy is high, every second to take a number, then after multiplication and division, FPGA function more. STM32 SPI communications are also used
Packet file list
(Preview for download)
dengjingdu
dengjingdu\control.bsf
dengjingdu\control.qpf
dengjingdu\control.qsf
dengjingdu\control.qws
dengjingdu\control.vhd
dengjingdu\counter_16.bsf
dengjingdu\counter_16.qpf
dengjingdu\counter_16.qsf
dengjingdu\counter_16.qws
dengjingdu\counter_16.vhd
dengjingdu\counter_16.vhd.bak
dengjingdu\counter_16_16_16.bdf
dengjingdu\counter_16_16_16.bsf
dengjingdu\counter_16_16_16.qpf
dengjingdu\counter_16_16_16.qsf
dengjingdu\counter_16_16_16.qws
dengjingdu\counter_8_8_8.bsf
dengjingdu\db
dengjingdu\db\control.asm.qmsg
dengjingdu\db\control.asm.rdb
dengjingdu\db\control.asm_labs.ddb
dengjingdu\db\control.cbx.xml
dengjingdu\db\control.cmp.bpm
dengjingdu\db\control.cmp.cdb
dengjingdu\db\control.cmp.hdb
dengjingdu\db\control.cmp.idb
dengjingdu\db\control.cmp.kpt
dengjingdu\db\control.cmp.logdb
dengjingdu\db\control.cmp.rdb
dengjingdu\db\control.cmp_merge.kpt
dengjingdu\db\control.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
dengjingdu\db\control.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
dengjingdu\db\control.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
dengjingdu\db\control.db_info
dengjingdu\db\control.fit.qmsg
dengjingdu\db\control.hier_info
dengjingdu\db\control.hif
dengjingdu\db\control.ipinfo
dengjingdu\db\control.lpc.html
dengjingdu\db\control.lpc.rdb
dengjingdu\db\control.lpc.txt
dengjingdu\db\control.map.ammdb
dengjingdu\db\control.map.bpm
dengjingdu\db\control.map.cdb
dengjingdu\db\control.map.hdb
dengjingdu\db\control.map.kpt
dengjingdu\db\control.map.logdb
dengjingdu\db\control.map.qmsg
dengjingdu\db\control.map.rdb
dengjingdu\db\control.map_bb.cdb
dengjingdu\db\control.map_bb.hdb
dengjingdu\db\control.map_bb.logdb
dengjingdu\db\control.pre_map.hdb
dengjingdu\db\control.pti_db_list.ddb
dengjingdu\db\control.root_partition.map.reg_db.cdb
dengjingdu\db\control.routing.rdb
dengjingdu\db\control.rtlv.hdb
dengjingdu\db\control.rtlv_sg.cdb
dengjingdu\db\control.rtlv_sg_swap.cdb
dengjingdu\db\control.sgdiff.cdb
dengjingdu\db\control.sgdiff.hdb
dengjingdu\db\control.sld_design_entry.sci
dengjingdu\db\control.sld_design_entry_dsc.sci
dengjingdu\db\control.smart_action.txt
dengjingdu\db\control.sta.qmsg
dengjingdu\db\control.sta.rdb
dengjingdu\db\control.sta_cmp.8_slow_1200mv_85c.tdb
dengjingdu\db\control.syn_hier_info
dengjingdu\db\control.tis_db_list.ddb
dengjingdu\db\control.tiscmp.fast_1200mv_0c.ddb
dengjingdu\db\control.tiscmp.fastest_slow_1200mv_0c.ddb
dengjingdu\db\control.tiscmp.fastest_slow_1200mv_85c.ddb
dengjingdu\db\control.tiscmp.slow_1200mv_0c.ddb
dengjingdu\db\control.tiscmp.slow_1200mv_85c.ddb
dengjingdu\db\control.tmw_info
dengjingdu\db\control.vpr.ammdb
dengjingdu\db\counter_16.asm.qmsg
dengjingdu\db\counter_16.asm.rdb
dengjingdu\db\counter_16.asm_labs.ddb
dengjingdu\db\counter_16.cbx.xml
dengjingdu\db\counter_16.cmp.bpm
dengjingdu\db\counter_16.cmp.cdb
dengjingdu\db\counter_16.cmp.hdb
dengjingdu\db\counter_16.cmp.idb
dengjingdu\db\counter_16.cmp.kpt
dengjingdu\db\counter_16.cmp.logdb
dengjingdu\db\counter_16.cmp.rdb
dengjingdu\db\counter_16.cmp_merge.kpt
dengjingdu\db\counter_16.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
dengjingdu\db\counter_16.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
dengjingdu\db\counter_16.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
dengjingdu\db\counter_16.db_info
dengjingdu\db\counter_16.fit.qmsg
dengjingdu\db\counter_16.hier_info
dengjingdu\db\counter_16.hif
dengjingdu\db\counter_16.ipinfo
dengjingdu\db\counter_16.lpc.html
dengjingdu\db\counter_16.lpc.rdb
dengjingdu\db\counter_16.lpc.txt
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