The transmission between different clock modules is realized by using FIFO module

FIFO_1\db\altsyncram_i211.tdf
FIFO_1\db\alt_synch_pipe_c7d.tdf
FIFO_1\db\alt_synch_pipe_d7d.tdf
FIFO_1\db\a_graycounter_07c.tdf
FIFO_1\db\a_graycounter_4p6.tdf
FIFO_1\db\cmpr_o76.tdf
FIFO_1\db\dcfifo_58h1.tdf
FIFO_1\db\dffpipe_b09.tdf
FIFO_1\db\dffpipe_c09.tdf
FIFO_1\db\logic_util_heursitic.dat
FIFO_1\db\prev_cmp_wr_fifo.qmsg
FIFO_1\db\wr_fifo.asm.qmsg
FIFO_1\db\wr_fifo.asm.rdb
FIFO_1\db\wr_fifo.asm_labs.ddb
FIFO_1\db\wr_fifo.cbx.xml
FIFO_1\db\wr_fifo.cmp.bpm
FIFO_1\db\wr_fifo.cmp.cdb
FIFO_1\db\wr_fifo.cmp.hdb
FIFO_1\db\wr_fifo.cmp.idb
FIFO_1\db\wr_fifo.cmp.kpt
FIFO_1\db\wr_fifo.cmp.logdb
FIFO_1\db\wr_fifo.cmp.rdb
FIFO_1\db\wr_fifo.cmp_merge.kpt
FIFO_1\db\wr_fifo.cycloneive_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
FIFO_1\db\wr_fifo.cycloneive_io_sim_cache.31um_ss_1200mv_0c_slow.hsd
FIFO_1\db\wr_fifo.cycloneive_io_sim_cache.31um_ss_1200mv_85c_slow.hsd
FIFO_1\db\wr_fifo.db_info
FIFO_1\db\wr_fifo.eda.qmsg
FIFO_1\db\wr_fifo.fit.qmsg
FIFO_1\db\wr_fifo.hier_info
FIFO_1\db\wr_fifo.hif
FIFO_1\db\wr_fifo.ipinfo
FIFO_1\db\wr_fifo.lpc.html
FIFO_1\db\wr_fifo.lpc.rdb
FIFO_1\db\wr_fifo.lpc.txt
FIFO_1\db\wr_fifo.map.ammdb
FIFO_1\db\wr_fifo.map.bpm
FIFO_1\db\wr_fifo.map.cdb
FIFO_1\db\wr_fifo.map.hdb
FIFO_1\db\wr_fifo.map.kpt
FIFO_1\db\wr_fifo.map.logdb
FIFO_1\db\wr_fifo.map.qmsg
FIFO_1\db\wr_fifo.map.rdb
FIFO_1\db\wr_fifo.map_bb.cdb
FIFO_1\db\wr_fifo.map_bb.hdb
FIFO_1\db\wr_fifo.map_bb.logdb
FIFO_1\db\wr_fifo.pre_map.hdb
FIFO_1\db\wr_fifo.pti_db_list.ddb
FIFO_1\db\wr_fifo.root_partition.map.reg_db.cdb
FIFO_1\db\wr_fifo.routing.rdb
FIFO_1\db\wr_fifo.rpp.qmsg
FIFO_1\db\wr_fifo.rtlv.hdb
FIFO_1\db\wr_fifo.rtlv_sg.cdb
FIFO_1\db\wr_fifo.rtlv_sg_swap.cdb
FIFO_1\db\wr_fifo.sgate.rvd
FIFO_1\db\wr_fifo.sgate_sm.rvd
FIFO_1\db\wr_fifo.sgdiff.cdb
FIFO_1\db\wr_fifo.sgdiff.hdb
FIFO_1\db\wr_fifo.sld_design_entry.sci
FIFO_1\db\wr_fifo.sld_design_entry_dsc.sci
FIFO_1\db\wr_fifo.smart_action.txt
FIFO_1\db\wr_fifo.sta.qmsg
FIFO_1\db\wr_fifo.sta.rdb
FIFO_1\db\wr_fifo.sta_cmp.8_slow_1200mv_85c.tdb
FIFO_1\db\wr_fifo.syn_hier_info
FIFO_1\db\wr_fifo.tiscmp.fastest_slow_1200mv_0c.ddb
FIFO_1\db\wr_fifo.tiscmp.fastest_slow_1200mv_85c.ddb
FIFO_1\db\wr_fifo.tiscmp.fast_1200mv_0c.ddb
FIFO_1\db\wr_fifo.tiscmp.slow_1200mv_0c.ddb
FIFO_1\db\wr_fifo.tiscmp.slow_1200mv_85c.ddb
FIFO_1\db\wr_fifo.tis_db_list.ddb
FIFO_1\db\wr_fifo.tmw_info
FIFO_1\db\wr_fifo.vpr.ammdb
FIFO_1\fifo.v
FIFO_1\fifo.v.bak
FIFO_1\greybox_tmp\cbx_args.txt
FIFO_1\incremental_db\compiled_partitions\wr_fifo.db_info
FIFO_1\incremental_db\compiled_partitions\wr_fifo.root_partition.cmp.ammdb
FIFO_1\incremental_db\compiled_partitions\wr_fifo.root_partition.cmp.cdb
FIFO_1\incremental_db\compiled_partitions\wr_fifo.root_partition.cmp.dfp
FIFO_1\incremental_db\compiled_partitions\wr_fifo.root_partition.cmp.hdb
FIFO_1\incremental_db\compiled_partitions\wr_fifo.root_partition.cmp.kpt
FIFO_1\incremental_db\compiled_partitions\wr_fifo.root_partition.cmp.logdb
FIFO_1\incremental_db\compiled_partitions\wr_fifo.root_partition.cmp.rcfdb
FIFO_1\incremental_db\compiled_partitions\wr_fifo.root_partition.map.cdb
FIFO_1\incremental_db\compiled_partitions\wr_fifo.root_partition.map.dpi
FIFO_1\incremental_db\compiled_partitions\wr_fifo.root_partition.map.hbdb.cdb
FIFO_1\incremental_db\compiled_partitions\wr_fifo.root_partition.map.hbdb.hb_info
FIFO_1\incremental_db\compiled_partitions\wr_fifo.root_partition.map.hbdb.hdb
FIFO_1\incremental_db\compiled_partitions\wr_fifo.root_partition.map.hbdb.sig
FIFO_1\incremental_db\compiled_partitions\wr_fifo.root_partition.map.hdb
FIFO_1\incremental_db\compiled_partitions\wr_fifo.root_partition.map.kpt
FIFO_1\incremental_db\README
FIFO_1\my_fifo.qip
FIFO_1\my_fifo.v
FIFO_1\my_fifo_bb.v
FIFO_1\my_fifo_inst.v
FIFO_1\output_files\wr_fifo.asm.rpt
FIFO_1\output_files\wr_fifo.done
FIFO_1\output_files\wr_fifo.eda.rpt

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