Verilog language based on DDS (digital frequency synthesizer) design, there is a complete engineering design code and simulation scripts

ex_DDS\design\ex_dds.v
ex_DDS\matlab\binary\gen_sin.m
ex_DDS\matlab\binary\rom_8x256.mif
ex_DDS\matlab\decimal\data.txt
ex_DDS\matlab\decimal\gen_sin.m
ex_DDS\matlab\decimal\rom_8x256.mif
ex_DDS\quartus_prj\db\ex_DDS.db_info
ex_DDS\quartus_prj\db\ex_DDS.eco.cdb
ex_DDS\quartus_prj\db\ex_DDS.ipinfo
ex_DDS\quartus_prj\db\ex_DDS.pplq.rdb
ex_DDS\quartus_prj\db\ex_DDS.sld_design_entry.sci
ex_DDS\quartus_prj\ex_DDS.qpf
ex_DDS\quartus_prj\ex_DDS.qsf
ex_DDS\quartus_prj\ex_DDS.qws
ex_DDS\quartus_prj\ipcore_dir\greybox_tmp\cbx_args.txt
ex_DDS\quartus_prj\ipcore_dir\rom_8x256.mif
ex_DDS\quartus_prj\ipcore_dir\rom_8x256.qip
ex_DDS\quartus_prj\ipcore_dir\rom_8x256.v
ex_DDS\quartus_prj\ipcore_dir\rom_8x256_inst.v
ex_DDS\quartus_prj\no_rev.pti_db_list.ddb
ex_DDS\quartus_prj\no_rev.tis_db_list.ddb
ex_DDS\sim\altera_lib\altera_mf.v
ex_DDS\sim\ex_dds.cr.mti
ex_DDS\sim\ex_dds.mpf
ex_DDS\sim\rom_8x256.mif
ex_DDS\sim\rom_8x256.ver
ex_DDS\sim\run.do
ex_DDS\sim\tb_ex_dds.v
ex_DDS\sim\vsim.wlf
ex_DDS\sim\work\_info
ex_DDS\sim\work\_lib.qdb
ex_DDS\sim\work\_lib1_5.qdb
ex_DDS\sim\work\_lib1_5.qpg
ex_DDS\sim\work\_lib1_5.qtl
ex_DDS\sim\work\_vmake
ex_DDS\quartus_prj\ipcore_dir\greybox_tmp
ex_DDS\matlab\binary
ex_DDS\matlab\decimal
ex_DDS\quartus_prj\db
ex_DDS\quartus_prj\ipcore_dir
ex_DDS\sim\altera_lib
ex_DDS\sim\work
ex_DDS\design
ex_DDS\matlab
ex_DDS\quartus_prj
ex_DDS\sim
ex_DDS

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