Describes how to implement 32 bit CPU in FPGA, involving the amount of IVERILOG source code

32位CPU IVERILOG源码\AZPR_RTL\bus\include\bus.h
32位CPU IVERILOG源码\AZPR_RTL\bus\rtl\bus.v
32位CPU IVERILOG源码\AZPR_RTL\bus\rtl\bus_addr_dec.v
32位CPU IVERILOG源码\AZPR_RTL\bus\rtl\bus_arbiter.v
32位CPU IVERILOG源码\AZPR_RTL\bus\rtl\bus_master_mux.v
32位CPU IVERILOG源码\AZPR_RTL\bus\rtl\bus_slave_mux.v
32位CPU IVERILOG源码\AZPR_RTL\cpu\include\cpu.h
32位CPU IVERILOG源码\AZPR_RTL\cpu\include\isa.h
32位CPU IVERILOG源码\AZPR_RTL\cpu\include\spm.h
32位CPU IVERILOG源码\AZPR_RTL\cpu\rtl\alu.v
32位CPU IVERILOG源码\AZPR_RTL\cpu\rtl\bus_if.v
32位CPU IVERILOG源码\AZPR_RTL\cpu\rtl\cpu.v
32位CPU IVERILOG源码\AZPR_RTL\cpu\rtl\ctrl.v
32位CPU IVERILOG源码\AZPR_RTL\cpu\rtl\decoder.v
32位CPU IVERILOG源码\AZPR_RTL\cpu\rtl\ex_reg.v
32位CPU IVERILOG源码\AZPR_RTL\cpu\rtl\ex_stage.v
32位CPU IVERILOG源码\AZPR_RTL\cpu\rtl\gpr.v
32位CPU IVERILOG源码\AZPR_RTL\cpu\rtl\id_reg.v
32位CPU IVERILOG源码\AZPR_RTL\cpu\rtl\id_stage.v
32位CPU IVERILOG源码\AZPR_RTL\cpu\rtl\if_reg.v
32位CPU IVERILOG源码\AZPR_RTL\cpu\rtl\if_stage.v
32位CPU IVERILOG源码\AZPR_RTL\cpu\rtl\mem_ctrl.v
32位CPU IVERILOG源码\AZPR_RTL\cpu\rtl\mem_reg.v
32位CPU IVERILOG源码\AZPR_RTL\cpu\rtl\mem_stage.v
32位CPU IVERILOG源码\AZPR_RTL\cpu\rtl\spm.v
32位CPU IVERILOG源码\AZPR_RTL\io\gpio\include\gpio.h
32位CPU IVERILOG源码\AZPR_RTL\io\gpio\rtl\gpio.v
32位CPU IVERILOG源码\AZPR_RTL\io\rom\include\rom.h
32位CPU IVERILOG源码\AZPR_RTL\io\rom\rtl\rom.v
32位CPU IVERILOG源码\AZPR_RTL\io\timer\include\timer.h
32位CPU IVERILOG源码\AZPR_RTL\io\timer\rtl\timer.v
32位CPU IVERILOG源码\AZPR_RTL\io\uart\include\uart.h
32位CPU IVERILOG源码\AZPR_RTL\io\uart\rtl\uart.v
32位CPU IVERILOG源码\AZPR_RTL\io\uart\rtl\uart_ctrl.v
32位CPU IVERILOG源码\AZPR_RTL\io\uart\rtl\uart_rx.v
32位CPU IVERILOG源码\AZPR_RTL\io\uart\rtl\uart_tx.v
32位CPU IVERILOG源码\AZPR_RTL\top\include\global_config.h
32位CPU IVERILOG源码\AZPR_RTL\top\include\nettype.h
32位CPU IVERILOG源码\AZPR_RTL\top\include\stddef.h
32位CPU IVERILOG源码\AZPR_RTL\top\lib\x_s3e_dcm.v
32位CPU IVERILOG源码\AZPR_RTL\top\lib\x_s3e_dpram.v
32位CPU IVERILOG源码\AZPR_RTL\top\lib\x_s3e_sprom.v
32位CPU IVERILOG源码\AZPR_RTL\top\rtl\chip.v
32位CPU IVERILOG源码\AZPR_RTL\top\rtl\chip_top.v
32位CPU IVERILOG源码\AZPR_RTL\top\rtl\clk_gen.v
32位CPU IVERILOG源码\AZPR_RTL\top\test\chip_top.out
32位CPU IVERILOG源码\AZPR_RTL\top\test\chip_top_test.v
32位CPU IVERILOG源码\AZPR_RTL\top\test\sim.cmd.txt
32位CPU IVERILOG源码\AZPR_RTL\top\test\test.dat
32位CPU IVERILOG源码\AZPR_RTL\io\gpio\include
32位CPU IVERILOG源码\AZPR_RTL\io\gpio\rtl
32位CPU IVERILOG源码\AZPR_RTL\io\rom\include
32位CPU IVERILOG源码\AZPR_RTL\io\rom\rtl
32位CPU IVERILOG源码\AZPR_RTL\io\timer\include
32位CPU IVERILOG源码\AZPR_RTL\io\timer\rtl
32位CPU IVERILOG源码\AZPR_RTL\io\uart\include
32位CPU IVERILOG源码\AZPR_RTL\io\uart\rtl
32位CPU IVERILOG源码\AZPR_RTL\bus\include
32位CPU IVERILOG源码\AZPR_RTL\bus\rtl
32位CPU IVERILOG源码\AZPR_RTL\cpu\include
32位CPU IVERILOG源码\AZPR_RTL\cpu\rtl
32位CPU IVERILOG源码\AZPR_RTL\io\gpio
32位CPU IVERILOG源码\AZPR_RTL\io\rom
32位CPU IVERILOG源码\AZPR_RTL\io\timer
32位CPU IVERILOG源码\AZPR_RTL\io\uart
32位CPU IVERILOG源码\AZPR_RTL\top\include
32位CPU IVERILOG源码\AZPR_RTL\top\lib
32位CPU IVERILOG源码\AZPR_RTL\top\rtl
32位CPU IVERILOG源码\AZPR_RTL\top\test
32位CPU IVERILOG源码\AZPR_RTL\bus
32位CPU IVERILOG源码\AZPR_RTL\cpu
32位CPU IVERILOG源码\AZPR_RTL\io
32位CPU IVERILOG源码\AZPR_RTL\top
32位CPU IVERILOG源码\AZPR_RTL
32位CPU IVERILOG源码

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