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Vivado Reference Design R1
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Category :
VHDL-FPGA-Verilog
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Update : 2017-08-14
Size : 2.22mb
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Author :
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vivado FPGA verilog VHDL
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Vivado Reference Design R1
Vivado Reference Design R1\amc516_fmc212.runs
Vivado Reference Design R1\amc516_fmc212.runs\impl_1
Vivado Reference Design R1\amc516_fmc212.runs\impl_1\amc516_fmc212_fpga.bit
Vivado Reference Design R1\amc516_fmc212.xpr
Vivado Reference Design R1\sources
Vivado Reference Design R1\sources\amc516
Vivado Reference Design R1\sources\amc516\amc516_fmc212.vhd
Vivado Reference Design R1\sources\amc516\amc516_impl.xdc
Vivado Reference Design R1\sources\amc516\amc516_pins.xdc
Vivado Reference Design R1\sources\amc516\bd
Vivado Reference Design R1\sources\amc516\bd\design_1
Vivado Reference Design R1\sources\amc516\bd\design_1\design_1.bd
Vivado Reference Design R1\sources\common
Vivado Reference Design R1\sources\common\amc_common_reg.vhd
Vivado Reference Design R1\sources\common\axi_gpio_32.vhd
Vivado Reference Design R1\sources\common\axi_lite_rd_fifo.vhd
Vivado Reference Design R1\sources\common\axi_spi_sdio.vhd
Vivado Reference Design R1\sources\common\fmc212.vhd
Vivado Reference Design R1\sources\common\iddr_common_clk.vhd
Vivado Reference Design R1\sources\common\ip_repo
Vivado Reference Design R1\sources\common\ip_repo\fsl_elbc_axi4lite_bridge
Vivado Reference Design R1\sources\common\ip_repo\fsl_elbc_axi4lite_bridge\component.xml
Vivado Reference Design R1\sources\common\ip_repo\fsl_elbc_axi4lite_bridge\fsl_elbc_axi4lite_bridge.vhd
Vivado Reference Design R1\sources\common\ip_repo\fsl_elbc_axi4lite_bridge\xgui
Vivado Reference Design R1\sources\common\ip_repo\fsl_elbc_axi4lite_bridge\xgui\fsl_elbc_axi4lite_bridge_v1_0.tcl
Vivado Reference Design R1\sources\common\jesd204_0_support.v
Vivado Reference Design R1\sources\common\vt_single_sync.vhd
Vivado Reference Design R1\sources\ip
Vivado Reference Design R1\sources\ip\vc7vx690tffg1761-1
Vivado Reference Design R1\sources\ip\vc7vx690tffg1761-1\axi_bram_ctrl_0
Vivado Reference Design R1\sources\ip\vc7vx690tffg1761-1\axi_bram_ctrl_0\axi_bram_ctrl_0.xci
Vivado Reference Design R1\sources\ip\vc7vx690tffg1761-1\axi_crossbar_0
Vivado Reference Design R1\sources\ip\vc7vx690tffg1761-1\axi_crossbar_0\axi_crossbar_0.xci
Vivado Reference Design R1\sources\ip\vc7vx690tffg1761-1\blk_mem_gen_0
Vivado Reference Design R1\sources\ip\vc7vx690tffg1761-1\blk_mem_gen_0\blk_mem_gen_0.xci
Vivado Reference Design R1\sources\ip\vc7vx690tffg1761-1\clk_wiz_1
Vivado Reference Design R1\sources\ip\vc7vx690tffg1761-1\clk_wiz_1\clk_wiz_1.xci
Vivado Reference Design R1\sources\ip\vc7vx690tffg1761-1\fifo_generator_0
Vivado Reference Design R1\sources\ip\vc7vx690tffg1761-1\fifo_generator_0\fifo_generator_0.xci
Vivado Reference Design R1\sources\ip\vc7vx690tffg1761-1\fifo_generator_loopback
Vivado Reference Design R1\sources\ip\vc7vx690tffg1761-1\fifo_generator_loopback\fifo_generator_loopback.xci
Vivado Reference Design R1\sources\ip\vc7vx690tffg1761-1\ila_0
Vivado Reference Design R1\sources\ip\vc7vx690tffg1761-1\ila_0\ila_0.xci
Vivado Reference Design R1\sources\ip\vc7vx690tffg1761-1\ila_0\ila_0.xml
Vivado Reference Design R1\sources\ip\vc7vx690tffg1761-1\ila_adc_data
Vivado Reference Design R1\sources\ip\vc7vx690tffg1761-1\ila_adc_data\ila_adc_data.xci
Vivado Reference Design R1\sources\ip\vc7vx690tffg1761-1\ila_adc_data\ila_adc_data.xml
Vivado Reference Design R1\sources\ip\vc7vx690tffg1761-1\jesd204_0
Vivado Reference Design R1\sources\ip\vc7vx690tffg1761-1\jesd204_0\jesd204_0.xci
Vivado Reference Design R1\sources\ip\vc7vx690tffg1761-1\jesd204_phy_0
Vivado Reference Design R1\sources\ip\vc7vx690tffg1761-1\jesd204_phy_0\jesd204_phy_0.xci
Vivado Reference Design R1\sources\sdk
Vivado Reference Design R1\sources\sdk\fmc212_tool
Vivado Reference Design R1\sources\sdk\fmc212_tool\.cproject
Vivado Reference Design R1\sources\sdk\fmc212_tool\.project
Vivado Reference Design R1\sources\sdk\fmc212_tool\Debug
Vivado Reference Design R1\sources\sdk\fmc212_tool\Debug\fmc212_tool.elf
Vivado Reference Design R1\sources\sdk\fmc212_tool\src
Vivado Reference Design R1\sources\sdk\fmc212_tool\src\cli.c
Vivado Reference Design R1\sources\sdk\fmc212_tool\src\cli.h
Vivado Reference Design R1\sources\sdk\fmc212_tool\src\dac39j82.h
Vivado Reference Design R1\sources\sdk\fmc212_tool\src\devices.c
Vivado Reference Design R1\sources\sdk\fmc212_tool\src\devices.h
Vivado Reference Design R1\sources\sdk\fmc212_tool\src\ev12as200azp.h
Vivado Reference Design R1\sources\sdk\fmc212_tool\src\fmc212.c
Vivado Reference Design R1\sources\sdk\fmc212_tool\src\fmc212.h
Vivado Reference Design R1\sources\sdk\fmc212_tool\src\fmc212_tool_drv
Vivado Reference Design R1\sources\sdk\fmc212_tool\src\fmc212_tool_lb
Vivado Reference Design R1\sources\sdk\fmc212_tool\src\fmc212_tool_mmap
Vivado Reference Design R1\sources\sdk\fmc212_tool\src\hmc835.h
Vivado Reference Design R1\sources\sdk\fmc212_tool\src\jesd204.h
Vivado Reference Design R1\sources\sdk\fmc212_tool\src\lmk04828.h
Vivado Reference Design R1\sources\sdk\fmc212_tool\src\lscript.ld
Vivado Reference Design R1\sources\sdk\fmc212_tool\src\Makefile
Vivado Reference Design R1\sources\sdk\fmc212_tool\src\p2040_pcie_driver
Vivado Reference Design R1\sources\sdk\fmc212_tool\src\p2040_pcie_driver\Makefile
Vivado Reference Design R1\sources\sdk\fmc212_tool\src\p2040_pcie_driver\vt_simple_pcie_drv.c
Vivado Reference Design R1\sources\sdk\fmc212_tool\src\p2040_pcie_driver\vt_simple_pcie_drv.h
Vivado Reference Design R1\sources\sdk\fmc212_tool\src\p2040_pcie_driver\vt_simple_pcie_drv.ko
Vivado Reference Design R1\sources\sdk\fmc212_tool\src\platform.c
Vivado Reference Design R1\sources\sdk\fmc212_tool\src\platform.h
Vivado Reference Design R1\sources\sdk\fmc212_tool\src\platform_config.h
Vivado Reference Design R1\sources\sdk\fmc212_tool\src\spi_sdio.c
Vivado Reference Design R1\sources\sdk\fmc212_tool\src\spi_sdio.h
Vivado Reference Design R1\sources\sdk\fmc212_tool\src\testclocks_10mhz_to_FMC_CLK2_BIDIR_amc516.sh
Vivado Reference Design R1\sources\sdk\fmc212_tool\src\tool_common.c
Vivado Reference Design R1\sources\sdk\fmc212_tool\src\tool_common.h
Vivado Reference Design R1\sources\sdk\fmc212_tool\src\vt_pcie_mmap.h
Vivado Reference Design R1\sources\sdk\fmc212_tool\src\vt_platform.c
Vivado Reference Design R1\sources\sdk\fmc212_tool\src\vt_platform.h
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