Altera avmm, Inc., PCIe DMA design example, applied successfully in actual engineering

SV_AVMM_DMA_DDR3_128M
SV_AVMM_DMA_DDR3_128M\altpcie_sv_hip_ast_hip_status_bridge.v
SV_AVMM_DMA_DDR3_128M\avgz_pinout.tcl
SV_AVMM_DMA_DDR3_128M\hip_status_hw.tcl
SV_AVMM_DMA_DDR3_128M\pcie_lib
SV_AVMM_DMA_DDR3_128M\pcie_lib\top
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\afi_mux_ddr3_ddrx.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_arbiter_acq.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_ddrx_addr_cmd.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_ddrx_addr_cmd_wrap.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_ddrx_arbiter.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_ddrx_axi_st_converter.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_ddrx_buffer.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_ddrx_buffer_manager.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_ddrx_burst_gen.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_ddrx_burst_tracking.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_ddrx_cmd_gen.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_ddrx_controller.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_ddrx_controller_st_top.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_ddrx_csr.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_ddrx_dataid_manager.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_ddrx_ddr2_odt_gen.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_ddrx_ddr3_odt_gen.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_ddrx_define.iv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_ddrx_ecc_decoder.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_ddrx_ecc_decoder_32_syn.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_ddrx_ecc_decoder_64_syn.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_ddrx_ecc_encoder.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_ddrx_ecc_encoder_32_syn.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_ddrx_ecc_encoder_64_syn.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_ddrx_ecc_encoder_decoder_wrapper.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_ddrx_fifo.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_ddrx_input_if.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_ddrx_list.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_ddrx_lpddr2_addr_cmd.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_ddrx_mm_st_converter.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_ddrx_odt_gen.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_ddrx_rank_timer.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_ddrx_rdata_path.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_ddrx_rdwr_data_tmg.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_ddrx_sideband.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_ddrx_tbp.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_ddrx_timing_param.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_ddrx_wdata_path.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_mem_if_nextgen_ddr3_controller_core.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_reset_ctrl_lego.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_reset_ctrl_tgx_cdrauto.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_arbiter.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_csr_common.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_csr_common_h.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_csr_pcs8g.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_csr_pcs8g_h.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_csr_selector.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_m2s.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_mgmt2dec.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig.sdc
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_adce.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_adce_datactrl_sv.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_adce_sv.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_analog.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_analog_sv.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_basic.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_cal_seq.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_cpu.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_cpu_irq_mapper.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_cpu_mm_interconnect_0.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_demux.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_demux_001.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_mux.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_mux_001.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_cpu_mm_interconnect_0_router.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_cpu_mm_interconnect_0_router_001.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_cpu_mm_interconnect_0_router_002.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_cpu_mm_interconnect_0_router_003.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_mux.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_mux_001.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_cpu_ram.hex
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_cpu_ram.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_cpu_reconfig_cpu.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_cpu_reconfig_cpu_rf_ram_a.mif
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_cpu_reconfig_cpu_rf_ram_b.mif
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_cpu_reconfig_cpu_test_bench.v
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_dcd.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_dcd_align_clk.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_dcd_cal.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_dcd_cal_sim_model.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_dcd_control.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_dcd_datapath.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_dcd_eye_width.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_dcd_get_sum.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_dcd_pll_reset.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_dcd_sv.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_dfe.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_dfe_adapt_tap_sim_sv.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_dfe_adapt_tap_sv.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_dfe_cal_sim_sv.sv
SV_AVMM_DMA_DDR3_128M\pcie_lib\top\synthesis\submodules\alt_xcvr_reconfig_dfe_cal_sv.sv

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