This paper is designed based on FPGA, described by Verilog HDL language in Galois field GF () on RS (6,4) encoder. Using the ISE software Verilog HDL language for each module is described, and then compile, simulation in software, the ultimate realization of the RS (6,4) encoding, after downloading by chipscope data acquisition, the analysis with the simulation results meet the design requirements.

RS\CDCRS.cdc
RS\decode.cmd_log
RS\decode.lso
RS\decode.ngc
RS\decode.ngr
RS\decode.prj
RS\decode.stx
RS\decode.syr
RS\decode.xst
RS\decode_xst.xrpt
RS\div_2HZ.cmd_log
RS\div_2HZ.lso
RS\div_2HZ.ngc
RS\div_2HZ.ngr
RS\div_2HZ.prj
RS\div_2HZ.stx
RS\div_2HZ.syr
RS\div_2HZ.xst
RS\div_2HZ_cs.blc
RS\div_2HZ_cs.ngc
RS\div_2HZ_envsettings.html
RS\div_2HZ_summary.html
RS\div_2HZ_xst.xrpt
RS\impact.xsl
RS\impact_impact.xwbt
RS\iseconfig\RS.projectmgr
RS\iseconfig\RS.xreport
RS\iseconfig\RS_TOP.xreport
RS\pa.fromNetlist.tcl
RS\par_usage_statistics.html
RS\planAhead.ngc2edif.log
RS\planAhead_pid3888.debug
RS\planAhead_pid4152.debug
RS\planAhead_pid4392.debug
RS\planAhead_pid5408.debug
RS\planAhead_pid8356.debug
RS\planAhead_run_1\planAhead.jou
RS\planAhead_run_1\planAhead.log
RS\planAhead_run_1\planAhead_run.log
RS\planAhead_run_2\planAhead.jou
RS\planAhead_run_2\planAhead.log
RS\planAhead_run_2\planAhead_run.log
RS\planAhead_run_2\RS.data\cache\RS_TOP_ngc_zx.edif
RS\planAhead_run_2\RS.data\constrs_1\fileset.xml
RS\planAhead_run_2\RS.data\runs\impl_1.psg
RS\planAhead_run_2\RS.data\runs\runs.xml
RS\planAhead_run_2\RS.data\sim_1\fileset.xml
RS\planAhead_run_2\RS.data\sources_1\fileset.xml
RS\planAhead_run_2\RS.data\wt\java_command_handlers.wdf
RS\planAhead_run_2\RS.data\wt\project.wpc
RS\planAhead_run_2\RS.data\wt\webtalk_pa.xml
RS\planAhead_run_2\RS.ppr
RS\planAhead_run_3\planAhead.jou
RS\planAhead_run_3\planAhead.log
RS\planAhead_run_3\planAhead_run.log
RS\planAhead_run_3\RS.data\cache\RS_TOP_ngc_zx.edif
RS\planAhead_run_3\RS.data\constrs_1\designprops.xml
RS\planAhead_run_3\RS.data\constrs_1\fileset.xml
RS\planAhead_run_3\RS.data\constrs_1\usercols.xml
RS\planAhead_run_3\RS.data\runs\impl_1.psg
RS\planAhead_run_3\RS.data\runs\runs.xml
RS\planAhead_run_3\RS.data\sim_1\fileset.xml
RS\planAhead_run_3\RS.data\sources_1\chipscope.xml
RS\planAhead_run_3\RS.data\sources_1\fileset.xml
RS\planAhead_run_3\RS.data\sources_1\ports.xml
RS\planAhead_run_3\RS.data\wt\java_command_handlers.wdf
RS\planAhead_run_3\RS.data\wt\project.wpc
RS\planAhead_run_3\RS.data\wt\webtalk_pa.xml
RS\planAhead_run_3\RS.ppr
RS\planAhead_run_4\planAhead.jou
RS\planAhead_run_4\planAhead.log
RS\planAhead_run_4\planAhead_run.log
RS\planAhead_run_4\RS.data\cache\RS_TOP_ngc_zx.edif
RS\planAhead_run_4\RS.data\constrs_1\fileset.xml
RS\planAhead_run_4\RS.data\runs\impl_1.psg
RS\planAhead_run_4\RS.data\runs\runs.xml
RS\planAhead_run_4\RS.data\sim_1\fileset.xml
RS\planAhead_run_4\RS.data\sources_1\fileset.xml
RS\planAhead_run_4\RS.data\wt\java_command_handlers.wdf
RS\planAhead_run_4\RS.data\wt\project.wpc
RS\planAhead_run_4\RS.data\wt\webtalk_pa.xml
RS\planAhead_run_4\RS.ppr
RS\planAhead_run_5\planAhead.jou
RS\planAhead_run_5\planAhead.log
RS\planAhead_run_5\planAhead_run.log
RS\planAhead_run_5\RS.data\cache\RS_TOP_ngc_zx.edif
RS\planAhead_run_5\RS.data\constrs_1\designprops.xml
RS\planAhead_run_5\RS.data\constrs_1\fileset.xml
RS\planAhead_run_5\RS.data\constrs_1\usercols.xml
RS\planAhead_run_5\RS.data\runs\impl_1.psg
RS\planAhead_run_5\RS.data\runs\runs.xml
RS\planAhead_run_5\RS.data\sim_1\fileset.xml
RS\planAhead_run_5\RS.data\sources_1\chipscope.xml
RS\planAhead_run_5\RS.data\sources_1\fileset.xml
RS\planAhead_run_5\RS.data\sources_1\ports.xml
RS\planAhead_run_5\RS.data\wt\java_command_handlers.wdf
RS\planAhead_run_5\RS.data\wt\project.wpc
RS\planAhead_run_5\RS.data\wt\webtalk_pa.xml
RS\planAhead_run_5\RS.ppr
RS\RS DOWNLOAD.ipf

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