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uart_test

  • Category : VHDL-FPGA-Verilog
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  • Update : 2017-08-28
  • Size : 227kb
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Introduction - If you have any usage issues, please Google them yourself
Serial communication on the UART code, pro test can be used for learning to use
Packet file list
(Preview for download)
uart_test
uart_test\uart_test
uart_test\uart_test\clkdiv.bsf
uart_test\uart_test\db
uart_test\uart_test\db\logic_util_heursitic.dat
uart_test\uart_test\db\prev_cmp_uart_test.qmsg
uart_test\uart_test\db\uart_test.db_info
uart_test\uart_test\db\uart_test.sld_design_entry.sci
uart_test\uart_test\incremental_db
uart_test\uart_test\incremental_db\README
uart_test\uart_test\incremental_db\compiled_partitions
uart_test\uart_test\incremental_db\compiled_partitions\uart_test.db_info
uart_test\uart_test\rtl
uart_test\uart_test\rtl\clkdiv.v
uart_test\uart_test\rtl\uart_test.bdf
uart_test\uart_test\rtl\uartrx.v
uart_test\uart_test\rtl\uartrx.v.bak
uart_test\uart_test\rtl\uarttx.v
uart_test\uart_test\rtl\uarttx.v.bak
uart_test\uart_test\uart_test.asm.rpt
uart_test\uart_test\uart_test.cdf
uart_test\uart_test\uart_test.done
uart_test\uart_test\uart_test.fit.rpt
uart_test\uart_test\uart_test.fit.smsg
uart_test\uart_test\uart_test.fit.summary
uart_test\uart_test\uart_test.flow.rpt
uart_test\uart_test\uart_test.jdi
uart_test\uart_test\uart_test.map.rpt
uart_test\uart_test\uart_test.map.summary
uart_test\uart_test\uart_test.pin
uart_test\uart_test\uart_test.qpf
uart_test\uart_test\uart_test.qsf
uart_test\uart_test\uart_test.qws
uart_test\uart_test\uart_test.sof
uart_test\uart_test\uart_test.sta.rpt
uart_test\uart_test\uart_test.sta.summary
uart_test\uart_test\uart_test_assignment_defaults.qdf
uart_test\uart_test\uartrx.bsf
uart_test\uart_test\uarttx.bsf
uart_test\uart_tx
uart_test\uart_tx\clkdiv.bsf
uart_test\uart_tx\db
uart_test\uart_tx\db\logic_util_heursitic.dat
uart_test\uart_tx\db\prev_cmp_uart_tx.qmsg
uart_test\uart_tx\db\uart_tx.db_info
uart_test\uart_tx\db\uart_tx.sld_design_entry.sci
uart_test\uart_tx\incremental_db
uart_test\uart_tx\incremental_db\README
uart_test\uart_tx\incremental_db\compiled_partitions
uart_test\uart_tx\incremental_db\compiled_partitions\uart_tx.db_info
uart_test\uart_tx\output_files
uart_test\uart_tx\output_files\uart_tx.asm.rpt
uart_test\uart_tx\output_files\uart_tx.done
uart_test\uart_tx\output_files\uart_tx.eda.rpt
uart_test\uart_tx\output_files\uart_tx.fit.rpt
uart_test\uart_tx\output_files\uart_tx.fit.smsg
uart_test\uart_tx\output_files\uart_tx.fit.summary
uart_test\uart_tx\output_files\uart_tx.flow.rpt
uart_test\uart_tx\output_files\uart_tx.jdi
uart_test\uart_tx\output_files\uart_tx.map.rpt
uart_test\uart_tx\output_files\uart_tx.map.summary
uart_test\uart_tx\output_files\uart_tx.pin
uart_test\uart_tx\output_files\uart_tx.sof
uart_test\uart_tx\output_files\uart_tx.sta.rpt
uart_test\uart_tx\output_files\uart_tx.sta.summary
uart_test\uart_tx\rtl
uart_test\uart_tx\rtl\clkdiv.v
uart_test\uart_tx\rtl\testuart.v
uart_test\uart_tx\rtl\testuart.v.bak
uart_test\uart_tx\rtl\uart_tx.bdf
uart_test\uart_tx\rtl\uarttx.v
uart_test\uart_tx\rtl\uarttx.v.bak
uart_test\uart_tx\simulation
uart_test\uart_tx\simulation\modelsim
uart_test\uart_tx\simulation\modelsim\uart_tx.sft
uart_test\uart_tx\simulation\modelsim\uart_tx.vho
uart_test\uart_tx\simulation\modelsim\uart_tx_8_1200mv_0c_slow.vho
uart_test\uart_tx\simulation\modelsim\uart_tx_8_1200mv_0c_vhd_slow.sdo
uart_test\uart_tx\simulation\modelsim\uart_tx_8_1200mv_85c_slow.vho
uart_test\uart_tx\simulation\modelsim\uart_tx_8_1200mv_85c_vhd_slow.sdo
uart_test\uart_tx\simulation\modelsim\uart_tx_min_1200mv_0c_fast.vho
uart_test\uart_tx\simulation\modelsim\uart_tx_min_1200mv_0c_vhd_fast.sdo
uart_test\uart_tx\simulation\modelsim\uart_tx_modelsim.xrf
uart_test\uart_tx\simulation\modelsim\uart_tx_vhd.sdo
uart_test\uart_tx\testuart.bsf
uart_test\uart_tx\uart_tx.jdi
uart_test\uart_tx\uart_tx.qpf
uart_test\uart_tx\uart_tx.qsf
uart_test\uart_tx\uart_tx.qws
uart_test\uart_tx\uart_tx.sdc
uart_test\uart_tx\uarttx.bsf
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