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Johnaon_counter

  • Category : VHDL-FPGA-Verilog
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  • Update : 2017-08-31
  • Size : 6kb
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  • Author :Leeg****
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Introduction - If you have any usage issues, please Google them yourself
This design is a six-bit Johnson counter, first of all to introduce what is the Johnson counter, it also called the torsion ring counter, is a kind of n-bit trigger to represent the 2n state of the counter. It differs from a ring counter, which uses n-bit triggers only to represent N states. The 2~n feed counter (n is the number of triggers) has a 2~n state. For example, a 6-bit binary counter can represent 64 states. However, because there may be two-bit or more than two bits of binary code between each set of code in 8421 yards, it is possible to produce the wrong decoding signal in the counter, especially in the asynchronous counter, resulting in a permanent error. In the state table of the Johnson counter, the adjacent two groups of code may only have one binary code, so there will be no wrong decoding signal in the counting process. In view of the above advantages, Johnson counter is widely used in synchronization counter.
Packet file list
(Preview for download)
Johnson_counter.ucf
Johnson_counter.v
usage_statistics_webtalk.html
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