SRAM read and write test instances, each time a single byte SRAM Read and write operations, use chipscope to see the timing waveform.

SRAM\counter.lso
SRAM\counter.prj
SRAM\counter.stx
SRAM\counter.xst
SRAM\ipcore_dir\chipscope_debug.cdc
SRAM\ipcore_dir\coregen.cgp
SRAM\ipcore_dir\coregen.log
SRAM\ipcore_dir\create_pll_controller.tcl
SRAM\ipcore_dir\edit_pll_controller.tcl
SRAM\ipcore_dir\pll_controller\clk_wiz_v3_6_readme.txt
SRAM\ipcore_dir\pll_controller\doc\clk_wiz_v3_6_readme.txt
SRAM\ipcore_dir\pll_controller\doc\clk_wiz_v3_6_vinfo.html
SRAM\ipcore_dir\pll_controller\doc\pg065_clk_wiz.pdf
SRAM\ipcore_dir\pll_controller\example_design\pll_controller_exdes.ucf
SRAM\ipcore_dir\pll_controller\example_design\pll_controller_exdes.v
SRAM\ipcore_dir\pll_controller\example_design\pll_controller_exdes.xdc
SRAM\ipcore_dir\pll_controller\implement\implement.bat
SRAM\ipcore_dir\pll_controller\implement\implement.sh
SRAM\ipcore_dir\pll_controller\implement\planAhead_ise.bat
SRAM\ipcore_dir\pll_controller\implement\planAhead_ise.sh
SRAM\ipcore_dir\pll_controller\implement\planAhead_ise.tcl
SRAM\ipcore_dir\pll_controller\implement\planAhead_rdn.bat
SRAM\ipcore_dir\pll_controller\implement\planAhead_rdn.sh
SRAM\ipcore_dir\pll_controller\implement\planAhead_rdn.tcl
SRAM\ipcore_dir\pll_controller\implement\xst.prj
SRAM\ipcore_dir\pll_controller\implement\xst.scr
SRAM\ipcore_dir\pll_controller\simulation\functional\simcmds.tcl
SRAM\ipcore_dir\pll_controller\simulation\functional\simulate_isim.bat
SRAM\ipcore_dir\pll_controller\simulation\functional\simulate_isim.sh
SRAM\ipcore_dir\pll_controller\simulation\functional\simulate_mti.bat
SRAM\ipcore_dir\pll_controller\simulation\functional\simulate_mti.do
SRAM\ipcore_dir\pll_controller\simulation\functional\simulate_mti.sh
SRAM\ipcore_dir\pll_controller\simulation\functional\simulate_ncsim.sh
SRAM\ipcore_dir\pll_controller\simulation\functional\simulate_vcs.sh
SRAM\ipcore_dir\pll_controller\simulation\functional\ucli_commands.key
SRAM\ipcore_dir\pll_controller\simulation\functional\vcs_session.tcl
SRAM\ipcore_dir\pll_controller\simulation\functional\wave.do
SRAM\ipcore_dir\pll_controller\simulation\functional\wave.sv
SRAM\ipcore_dir\pll_controller\simulation\pll_controller_tb.v
SRAM\ipcore_dir\pll_controller\simulation\timing\pll_controller_tb.v
SRAM\ipcore_dir\pll_controller\simulation\timing\sdf_cmd_file
SRAM\ipcore_dir\pll_controller\simulation\timing\simcmds.tcl
SRAM\ipcore_dir\pll_controller\simulation\timing\simulate_isim.sh
SRAM\ipcore_dir\pll_controller\simulation\timing\simulate_mti.bat
SRAM\ipcore_dir\pll_controller\simulation\timing\simulate_mti.do
SRAM\ipcore_dir\pll_controller\simulation\timing\simulate_mti.sh
SRAM\ipcore_dir\pll_controller\simulation\timing\simulate_ncsim.sh
SRAM\ipcore_dir\pll_controller\simulation\timing\simulate_vcs.sh
SRAM\ipcore_dir\pll_controller\simulation\timing\ucli_commands.key
SRAM\ipcore_dir\pll_controller\simulation\timing\vcs_session.tcl
SRAM\ipcore_dir\pll_controller\simulation\timing\wave.do
SRAM\ipcore_dir\pll_controller.asy
SRAM\ipcore_dir\pll_controller.gise
SRAM\ipcore_dir\pll_controller.ncf
SRAM\ipcore_dir\pll_controller.sym
SRAM\ipcore_dir\pll_controller.ucf
SRAM\ipcore_dir\pll_controller.v
SRAM\ipcore_dir\pll_controller.veo
SRAM\ipcore_dir\pll_controller.xco
SRAM\ipcore_dir\pll_controller.xdc
SRAM\ipcore_dir\pll_controller.xise
SRAM\ipcore_dir\pll_controller_flist.txt
SRAM\ipcore_dir\pll_controller_xmdf.tcl
SRAM\ipcore_dir\tmp\customization_gui.0.0535084526304.out
SRAM\ipcore_dir\tmp\customization_gui.0.27564817121.out
SRAM\ipcore_dir\tmp\_cg\_dbg\xil_331.in
SRAM\ipcore_dir\tmp\_cg\_dbg\xil_331.out
SRAM\ipcore_dir\tmp\_xmsgs\pn_parser.xmsgs
SRAM\ipcore_dir\_xmsgs\cg.xmsgs
SRAM\ipcore_dir\_xmsgs\pn_parser.xmsgs
SRAM\iseconfig\sp6.projectmgr
SRAM\iseconfig\sp6.xreport
SRAM\led_controller.lso
SRAM\led_controller.prj
SRAM\led_controller.stx
SRAM\led_controller.xst
SRAM\modelsim.ini
SRAM\pa.fromHdl.tcl
SRAM\par_usage_statistics.html
SRAM\planAhead_pid10348.debug
SRAM\planAhead_pid1052.debug
SRAM\planAhead_pid8104.debug
SRAM\planAhead_pid8904.debug
SRAM\planAhead_pid9948.debug
SRAM\planAhead_run_1\planAhead.jou
SRAM\planAhead_run_1\planAhead.log
SRAM\planAhead_run_1\planAhead_run.log
SRAM\planAhead_run_1\sp6.data\constrs_1\fileset.xml
SRAM\planAhead_run_1\sp6.data\sim_1\fileset.xml
SRAM\planAhead_run_1\sp6.data\sources_1\fileset.xml
SRAM\planAhead_run_1\sp6.data\wt\project.wpc
SRAM\planAhead_run_1\sp6.data\wt\webtalk_pa.xml
SRAM\planAhead_run_1\sp6.ppr
SRAM\planAhead_run_2\planAhead.jou
SRAM\planAhead_run_2\planAhead.log
SRAM\planAhead_run_2\planAhead_run.log
SRAM\planAhead_run_2\sp6.data\constrs_1\fileset.xml
SRAM\planAhead_run_2\sp6.data\sim_1\fileset.xml
SRAM\planAhead_run_2\sp6.data\sources_1\fileset.xml
SRAM\planAhead_run_2\sp6.data\wt\project.wpc

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