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  • Category : VHDL-FPGA-Verilog
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  • Update : 2017-09-07
  • Size : 154kb
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  • Author :蜂蜜***
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Introduction - If you have any usage issues, please Google them yourself
ALTERA official board DE2 official code, the chip is EP2C35F672C6N
Packet file list
(Preview for download)
vip_ex18
vip_ex18\alt_mem_ddrx_addr_cmd.v
vip_ex18\alt_mem_ddrx_addr_cmd_wrap.v
vip_ex18\alt_mem_ddrx_arbiter.v
vip_ex18\alt_mem_ddrx_buffer.v
vip_ex18\alt_mem_ddrx_buffer_manager.v
vip_ex18\alt_mem_ddrx_burst_gen.v
vip_ex18\alt_mem_ddrx_burst_tracking.v
vip_ex18\alt_mem_ddrx_cmd_gen.v
vip_ex18\alt_mem_ddrx_controller.v
vip_ex18\alt_mem_ddrx_controller_st_top.v
vip_ex18\alt_mem_ddrx_csr.v
vip_ex18\alt_mem_ddrx_dataid_manager.v
vip_ex18\alt_mem_ddrx_ddr2_odt_gen.v
vip_ex18\alt_mem_ddrx_ddr3_odt_gen.v
vip_ex18\alt_mem_ddrx_define.iv
vip_ex18\alt_mem_ddrx_ecc_decoder.v
vip_ex18\alt_mem_ddrx_ecc_decoder_32_syn.v
vip_ex18\alt_mem_ddrx_ecc_decoder_64_syn.v
vip_ex18\alt_mem_ddrx_ecc_encoder.v
vip_ex18\alt_mem_ddrx_ecc_encoder_32_syn.v
vip_ex18\alt_mem_ddrx_ecc_encoder_64_syn.v
vip_ex18\alt_mem_ddrx_ecc_encoder_decoder_wrapper.v
vip_ex18\alt_mem_ddrx_fifo.v
vip_ex18\alt_mem_ddrx_input_if.v
vip_ex18\alt_mem_ddrx_list.v
vip_ex18\alt_mem_ddrx_lpddr2_addr_cmd.v
vip_ex18\alt_mem_ddrx_mm_st_converter.v
vip_ex18\alt_mem_ddrx_odt_gen.v
vip_ex18\alt_mem_ddrx_rank_timer.v
vip_ex18\alt_mem_ddrx_rdata_path.v
vip_ex18\alt_mem_ddrx_rdwr_data_tmg.v
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