An example design of Zynq GPIO (zynq7010 board)

CH10_AXI_User_GPIO\DOC\AXI4整理.doc
CH10_AXI_User_GPIO\DOC\MiZ7010N_CORE_20161215.pdf
CH10_AXI_User_GPIO\DOC\Miz701N_fun20161215.pdf
CH10_AXI_User_GPIO\DOC\readme.txt
CH10_AXI_User_GPIO\DOC\ug585-Zynq-7000-TRM.pdf
CH10_AXI_User_GPIO\Miz_ip_lib\GPIO_LITE_ML\component.xml
CH10_AXI_User_GPIO\Miz_ip_lib\GPIO_LITE_ML\GPIO_LITE_ML\GPIO_LITE_ML.cache\wt\java_command_handlers.wdf
CH10_AXI_User_GPIO\Miz_ip_lib\GPIO_LITE_ML\GPIO_LITE_ML\GPIO_LITE_ML.cache\wt\project.wpc
CH10_AXI_User_GPIO\Miz_ip_lib\GPIO_LITE_ML\GPIO_LITE_ML\GPIO_LITE_ML.cache\wt\synthesis.wdf
CH10_AXI_User_GPIO\Miz_ip_lib\GPIO_LITE_ML\GPIO_LITE_ML\GPIO_LITE_ML.cache\wt\synthesis_details.wdf
CH10_AXI_User_GPIO\Miz_ip_lib\GPIO_LITE_ML\GPIO_LITE_ML\GPIO_LITE_ML.cache\wt\webtalk_pa.xml
CH10_AXI_User_GPIO\Miz_ip_lib\GPIO_LITE_ML\GPIO_LITE_ML\GPIO_LITE_ML.hw\GPIO_LITE_ML.lpr
CH10_AXI_User_GPIO\Miz_ip_lib\GPIO_LITE_ML\GPIO_LITE_ML\GPIO_LITE_ML.runs\.jobs\vrs_config_1.xml
CH10_AXI_User_GPIO\Miz_ip_lib\GPIO_LITE_ML\GPIO_LITE_ML\GPIO_LITE_ML.runs\synth_1\.vivado.begin.rst
CH10_AXI_User_GPIO\Miz_ip_lib\GPIO_LITE_ML\GPIO_LITE_ML\GPIO_LITE_ML.runs\synth_1\.vivado.end.rst
CH10_AXI_User_GPIO\Miz_ip_lib\GPIO_LITE_ML\GPIO_LITE_ML\GPIO_LITE_ML.runs\synth_1\.Vivado_Synthesis.queue.rst
CH10_AXI_User_GPIO\Miz_ip_lib\GPIO_LITE_ML\GPIO_LITE_ML\GPIO_LITE_ML.runs\synth_1\gen_run.xml
CH10_AXI_User_GPIO\Miz_ip_lib\GPIO_LITE_ML\GPIO_LITE_ML\GPIO_LITE_ML.runs\synth_1\GPIO_LITE_ML.dcp
CH10_AXI_User_GPIO\Miz_ip_lib\GPIO_LITE_ML\GPIO_LITE_ML\GPIO_LITE_ML.runs\synth_1\GPIO_LITE_ML.tcl
CH10_AXI_User_GPIO\Miz_ip_lib\GPIO_LITE_ML\GPIO_LITE_ML\GPIO_LITE_ML.runs\synth_1\GPIO_LITE_ML.vds
CH10_AXI_User_GPIO\Miz_ip_lib\GPIO_LITE_ML\GPIO_LITE_ML\GPIO_LITE_ML.runs\synth_1\GPIO_LITE_ML_utilization_synth.pb
CH10_AXI_User_GPIO\Miz_ip_lib\GPIO_LITE_ML\GPIO_LITE_ML\GPIO_LITE_ML.runs\synth_1\GPIO_LITE_ML_utilization_synth.rpt
CH10_AXI_User_GPIO\Miz_ip_lib\GPIO_LITE_ML\GPIO_LITE_ML\GPIO_LITE_ML.runs\synth_1\htr.txt
CH10_AXI_User_GPIO\Miz_ip_lib\GPIO_LITE_ML\GPIO_LITE_ML\GPIO_LITE_ML.runs\synth_1\ISEWrap.js
CH10_AXI_User_GPIO\Miz_ip_lib\GPIO_LITE_ML\GPIO_LITE_ML\GPIO_LITE_ML.runs\synth_1\ISEWrap.sh
CH10_AXI_User_GPIO\Miz_ip_lib\GPIO_LITE_ML\GPIO_LITE_ML\GPIO_LITE_ML.runs\synth_1\project.wdf
CH10_AXI_User_GPIO\Miz_ip_lib\GPIO_LITE_ML\GPIO_LITE_ML\GPIO_LITE_ML.runs\synth_1\rundef.js
CH10_AXI_User_GPIO\Miz_ip_lib\GPIO_LITE_ML\GPIO_LITE_ML\GPIO_LITE_ML.runs\synth_1\runme.bat
CH10_AXI_User_GPIO\Miz_ip_lib\GPIO_LITE_ML\GPIO_LITE_ML\GPIO_LITE_ML.runs\synth_1\runme.log
CH10_AXI_User_GPIO\Miz_ip_lib\GPIO_LITE_ML\GPIO_LITE_ML\GPIO_LITE_ML.runs\synth_1\runme.sh
CH10_AXI_User_GPIO\Miz_ip_lib\GPIO_LITE_ML\GPIO_LITE_ML\GPIO_LITE_ML.runs\synth_1\vivado.jou
CH10_AXI_User_GPIO\Miz_ip_lib\GPIO_LITE_ML\GPIO_LITE_ML\GPIO_LITE_ML.runs\synth_1\vivado.pb
CH10_AXI_User_GPIO\Miz_ip_lib\GPIO_LITE_ML\GPIO_LITE_ML\GPIO_LITE_ML.xpr
CH10_AXI_User_GPIO\Miz_ip_lib\GPIO_LITE_ML\GPIO_LITE_ML\vivado.jou
CH10_AXI_User_GPIO\Miz_ip_lib\GPIO_LITE_ML\GPIO_LITE_ML\vivado.log
CH10_AXI_User_GPIO\Miz_ip_lib\GPIO_LITE_ML\IPSRC\GPIO_LITE_ML.v
CH10_AXI_User_GPIO\Miz_ip_lib\GPIO_LITE_ML\IPSRC\GPIO_LITE_ML_v1_0_S00_AXI.v
CH10_AXI_User_GPIO\Miz_ip_lib\GPIO_LITE_ML\xgui\GPIO_LITE_ML_v1_0.tcl
CH10_AXI_User_GPIO\Miz_ip_lib\LED_ML\component.xml
CH10_AXI_User_GPIO\Miz_ip_lib\LED_ML\IPSRC\LED_ML.v
CH10_AXI_User_GPIO\Miz_ip_lib\LED_ML\Miz_ip\Miz_ip.cache\wt\java_command_handlers.wdf
CH10_AXI_User_GPIO\Miz_ip_lib\LED_ML\Miz_ip\Miz_ip.cache\wt\project.wpc
CH10_AXI_User_GPIO\Miz_ip_lib\LED_ML\Miz_ip\Miz_ip.cache\wt\synthesis.wdf
CH10_AXI_User_GPIO\Miz_ip_lib\LED_ML\Miz_ip\Miz_ip.cache\wt\synthesis_details.wdf
CH10_AXI_User_GPIO\Miz_ip_lib\LED_ML\Miz_ip\Miz_ip.cache\wt\webtalk_pa.xml
CH10_AXI_User_GPIO\Miz_ip_lib\LED_ML\Miz_ip\Miz_ip.hw\Miz_ip.lpr
CH10_AXI_User_GPIO\Miz_ip_lib\LED_ML\Miz_ip\Miz_ip.runs\.jobs\vrs_config_1.xml
CH10_AXI_User_GPIO\Miz_ip_lib\LED_ML\Miz_ip\Miz_ip.runs\.jobs\vrs_config_2.xml
CH10_AXI_User_GPIO\Miz_ip_lib\LED_ML\Miz_ip\Miz_ip.runs\synth_1\.vivado.begin.rst
CH10_AXI_User_GPIO\Miz_ip_lib\LED_ML\Miz_ip\Miz_ip.runs\synth_1\.vivado.end.rst
CH10_AXI_User_GPIO\Miz_ip_lib\LED_ML\Miz_ip\Miz_ip.runs\synth_1\.Vivado_Synthesis.queue.rst
CH10_AXI_User_GPIO\Miz_ip_lib\LED_ML\Miz_ip\Miz_ip.runs\synth_1\gen_run.xml
CH10_AXI_User_GPIO\Miz_ip_lib\LED_ML\Miz_ip\Miz_ip.runs\synth_1\htr.txt
CH10_AXI_User_GPIO\Miz_ip_lib\LED_ML\Miz_ip\Miz_ip.runs\synth_1\ISEWrap.js
CH10_AXI_User_GPIO\Miz_ip_lib\LED_ML\Miz_ip\Miz_ip.runs\synth_1\ISEWrap.sh
CH10_AXI_User_GPIO\Miz_ip_lib\LED_ML\Miz_ip\Miz_ip.runs\synth_1\LED_ML.dcp
CH10_AXI_User_GPIO\Miz_ip_lib\LED_ML\Miz_ip\Miz_ip.runs\synth_1\LED_ML.tcl
CH10_AXI_User_GPIO\Miz_ip_lib\LED_ML\Miz_ip\Miz_ip.runs\synth_1\LED_ML.vds
CH10_AXI_User_GPIO\Miz_ip_lib\LED_ML\Miz_ip\Miz_ip.runs\synth_1\LED_ML_utilization_synth.pb
CH10_AXI_User_GPIO\Miz_ip_lib\LED_ML\Miz_ip\Miz_ip.runs\synth_1\LED_ML_utilization_synth.rpt
CH10_AXI_User_GPIO\Miz_ip_lib\LED_ML\Miz_ip\Miz_ip.runs\synth_1\project.wdf
CH10_AXI_User_GPIO\Miz_ip_lib\LED_ML\Miz_ip\Miz_ip.runs\synth_1\rundef.js
CH10_AXI_User_GPIO\Miz_ip_lib\LED_ML\Miz_ip\Miz_ip.runs\synth_1\runme.bat
CH10_AXI_User_GPIO\Miz_ip_lib\LED_ML\Miz_ip\Miz_ip.runs\synth_1\runme.log
CH10_AXI_User_GPIO\Miz_ip_lib\LED_ML\Miz_ip\Miz_ip.runs\synth_1\runme.sh
CH10_AXI_User_GPIO\Miz_ip_lib\LED_ML\Miz_ip\Miz_ip.runs\synth_1\vivado.jou
CH10_AXI_User_GPIO\Miz_ip_lib\LED_ML\Miz_ip\Miz_ip.runs\synth_1\vivado.pb
CH10_AXI_User_GPIO\Miz_ip_lib\LED_ML\Miz_ip\Miz_ip.xpr
CH10_AXI_User_GPIO\Miz_ip_lib\LED_ML\Miz_ip\vivado.jou
CH10_AXI_User_GPIO\Miz_ip_lib\LED_ML\Miz_ip\vivado.log
CH10_AXI_User_GPIO\Miz_ip_lib\LED_ML\xgui\LED_ML_v1_0.tcl
CH10_AXI_User_GPIO\Miz_sys\.Xil\system_wrapper_propImpl.xdc
CH10_AXI_User_GPIO\Miz_sys\Miz_sys.cache\wt\project.wpc
CH10_AXI_User_GPIO\Miz_sys\Miz_sys.cache\wt\synthesis.wdf
CH10_AXI_User_GPIO\Miz_sys\Miz_sys.cache\wt\synthesis_details.wdf
CH10_AXI_User_GPIO\Miz_sys\Miz_sys.cache\wt\webtalk_pa.xml
CH10_AXI_User_GPIO\Miz_sys\Miz_sys.hw\Miz_sys.lpr
CH10_AXI_User_GPIO\Miz_sys\Miz_sys.ip_user_files\bd\system\hdl\system.v
CH10_AXI_User_GPIO\Miz_sys\Miz_sys.ip_user_files\bd\system\ip\system_auto_pc_0\sim\system_auto_pc_0.v
CH10_AXI_User_GPIO\Miz_sys\Miz_sys.ip_user_files\bd\system\ip\system_GPIO_LITE_ML_0_0\sim\system_GPIO_LITE_ML_0_0.v
CH10_AXI_User_GPIO\Miz_sys\Miz_sys.ip_user_files\bd\system\ip\system_LED_ML_0_0\sim\system_LED_ML_0_0.v
CH10_AXI_User_GPIO\Miz_sys\Miz_sys.ip_user_files\bd\system\ip\system_processing_system7_0_0\sim\system_processing_system7_0_0.v
CH10_AXI_User_GPIO\Miz_sys\Miz_sys.ip_user_files\bd\system\ip\system_rst_processing_system7_0_100M_0\sim\system_rst_processing_system7_0_100M_0.vhd
CH10_AXI_User_GPIO\Miz_sys\Miz_sys.ip_user_files\ipstatic\axi_data_fifo_v2_1\hdl\verilog\axi_data_fifo_v2_1_axic_fifo.v
CH10_AXI_User_GPIO\Miz_sys\Miz_sys.ip_user_files\ipstatic\axi_data_fifo_v2_1\hdl\verilog\axi_data_fifo_v2_1_axic_reg_srl_fifo.v
CH10_AXI_User_GPIO\Miz_sys\Miz_sys.ip_user_files\ipstatic\axi_data_fifo_v2_1\hdl\verilog\axi_data_fifo_v2_1_axic_srl_fifo.v
CH10_AXI_User_GPIO\Miz_sys\Miz_sys.ip_user_files\ipstatic\axi_data_fifo_v2_1\hdl\verilog\axi_data_fifo_v2_1_axi_data_fifo.v
CH10_AXI_User_GPIO\Miz_sys\Miz_sys.ip_user_files\ipstatic\axi_data_fifo_v2_1\hdl\verilog\axi_data_fifo_v2_1_fifo_gen.v
CH10_AXI_User_GPIO\Miz_sys\Miz_sys.ip_user_files\ipstatic\axi_data_fifo_v2_1\hdl\verilog\axi_data_fifo_v2_1_ndeep_srl.v
CH10_AXI_User_GPIO\Miz_sys\Miz_sys.ip_user_files\ipstatic\axi_infrastructure_v1_1\hdl\verilog\axi_infrastructure_v1_1_0_header.vh
CH10_AXI_User_GPIO\Miz_sys\Miz_sys.ip_user_files\ipstatic\axi_infrastructure_v1_1\hdl\verilog\axi_infrastructure_v1_1_axi2vector.v
CH10_AXI_User_GPIO\Miz_sys\Miz_sys.ip_user_files\ipstatic\axi_infrastructure_v1_1\hdl\verilog\axi_infrastructure_v1_1_axic_srl_fifo.v
CH10_AXI_User_GPIO\Miz_sys\Miz_sys.ip_user_files\ipstatic\axi_infrastructure_v1_1\hdl\verilog\axi_infrastructure_v1_1_vector2axi.v
CH10_AXI_User_GPIO\Miz_sys\Miz_sys.ip_user_files\ipstatic\axi_protocol_converter_v2_1\hdl\verilog\axi_protocol_converter_v2_1_axi3_conv.v
CH10_AXI_User_GPIO\Miz_sys\Miz_sys.ip_user_files\ipstatic\axi_protocol_converter_v2_1\hdl\verilog\axi_protocol_converter_v2_1_axilite_conv.v
CH10_AXI_User_GPIO\Miz_sys\Miz_sys.ip_user_files\ipstatic\axi_protocol_converter_v2_1\hdl\verilog\axi_protocol_converter_v2_1_axi_protocol_converter.v
CH10_AXI_User_GPIO\Miz_sys\Miz_sys.ip_user_files\ipstatic\axi_protocol_converter_v2_1\hdl\verilog\axi_protocol_converter_v2_1_a_axi3_conv.v
CH10_AXI_User_GPIO\Miz_sys\Miz_sys.ip_user_files\ipstatic\axi_protocol_converter_v2_1\hdl\verilog\axi_protocol_converter_v2_1_b2s.v
CH10_AXI_User_GPIO\Miz_sys\Miz_sys.ip_user_files\ipstatic\axi_protocol_converter_v2_1\hdl\verilog\axi_protocol_converter_v2_1_b2s_ar_channel.v
CH10_AXI_User_GPIO\Miz_sys\Miz_sys.ip_user_files\ipstatic\axi_protocol_converter_v2_1\hdl\verilog\axi_protocol_converter_v2_1_b2s_aw_channel.v

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