FPGA based VGA experimental testing and a variety of code, in the hope that we can help!

VGA\15041741周涛EDA2.docx
VGA\2016下_实验2.docx
VGA\EDA_2.bmp
VGA\PICTURE.png
VGA\TASK_1\db\.cmp.kpt
VGA\TASK_1\db\logic_util_heursitic.dat
VGA\TASK_1\db\PLL_altpll.v
VGA\TASK_1\db\prev_cmp_TOP.qmsg
VGA\TASK_1\db\TOP.db_info
VGA\TASK_1\db\TOP.ipinfo
VGA\TASK_1\db\TOP.sld_design_entry.sci
VGA\TASK_1\greybox_tmp\cbx_args.txt
VGA\TASK_1\incremental_db\compiled_partitions\TOP.db_info
VGA\TASK_1\incremental_db\README
VGA\TASK_1\output_files\Chain4.cdf
VGA\TASK_1\output_files\Chain5.cdf
VGA\TASK_1\output_files\TOP.asm.rpt
VGA\TASK_1\output_files\TOP.cdf
VGA\TASK_1\output_files\TOP.done
VGA\TASK_1\output_files\TOP.eda.rpt
VGA\TASK_1\output_files\TOP.fit.rpt
VGA\TASK_1\output_files\TOP.fit.smsg
VGA\TASK_1\output_files\TOP.fit.summary
VGA\TASK_1\output_files\TOP.flow.rpt
VGA\TASK_1\output_files\TOP.jdi
VGA\TASK_1\output_files\TOP.map.rpt
VGA\TASK_1\output_files\TOP.map.summary
VGA\TASK_1\output_files\TOP.pin
VGA\TASK_1\output_files\TOP.sof
VGA\TASK_1\output_files\TOP.sta.rpt
VGA\TASK_1\output_files\TOP.sta.summary
VGA\TASK_1\PLL.ppf
VGA\TASK_1\PLL.qip
VGA\TASK_1\PLL.v
VGA\TASK_1\PLLJ_PLLSPE_INFO.txt
VGA\TASK_1\PLL_bb.v
VGA\TASK_1\simulation\modelsim\modelsim.ini
VGA\TASK_1\simulation\modelsim\msim_transcript
VGA\TASK_1\simulation\modelsim\rtl_work\@p@l@l\verilog.prw
VGA\TASK_1\simulation\modelsim\rtl_work\@p@l@l\verilog.psm
VGA\TASK_1\simulation\modelsim\rtl_work\@p@l@l\_primary.dat
VGA\TASK_1\simulation\modelsim\rtl_work\@p@l@l\_primary.dbs
VGA\TASK_1\simulation\modelsim\rtl_work\@p@l@l\_primary.vhd
VGA\TASK_1\simulation\modelsim\rtl_work\@p@l@l_altpll\verilog.prw
VGA\TASK_1\simulation\modelsim\rtl_work\@p@l@l_altpll\verilog.psm
VGA\TASK_1\simulation\modelsim\rtl_work\@p@l@l_altpll\_primary.dat
VGA\TASK_1\simulation\modelsim\rtl_work\@p@l@l_altpll\_primary.dbs
VGA\TASK_1\simulation\modelsim\rtl_work\@p@l@l_altpll\_primary.vhd
VGA\TASK_1\simulation\modelsim\rtl_work\@t@o@p\verilog.prw
VGA\TASK_1\simulation\modelsim\rtl_work\@t@o@p\verilog.psm
VGA\TASK_1\simulation\modelsim\rtl_work\@t@o@p\_primary.dat
VGA\TASK_1\simulation\modelsim\rtl_work\@t@o@p\_primary.dbs
VGA\TASK_1\simulation\modelsim\rtl_work\@t@o@p\_primary.vhd
VGA\TASK_1\simulation\modelsim\rtl_work\sync_module\verilog.prw
VGA\TASK_1\simulation\modelsim\rtl_work\sync_module\verilog.psm
VGA\TASK_1\simulation\modelsim\rtl_work\sync_module\_primary.dat
VGA\TASK_1\simulation\modelsim\rtl_work\sync_module\_primary.dbs
VGA\TASK_1\simulation\modelsim\rtl_work\sync_module\_primary.vhd
VGA\TASK_1\simulation\modelsim\rtl_work\vga_control_module\verilog.prw
VGA\TASK_1\simulation\modelsim\rtl_work\vga_control_module\verilog.psm
VGA\TASK_1\simulation\modelsim\rtl_work\vga_control_module\_primary.dat
VGA\TASK_1\simulation\modelsim\rtl_work\vga_control_module\_primary.dbs
VGA\TASK_1\simulation\modelsim\rtl_work\vga_control_module\_primary.vhd
VGA\TASK_1\simulation\modelsim\rtl_work\_info
VGA\TASK_1\simulation\modelsim\rtl_work\_vmake
VGA\TASK_1\simulation\modelsim\TOP.sft
VGA\TASK_1\simulation\modelsim\TOP.vo
VGA\TASK_1\simulation\modelsim\TOP_8_1200mv_0c_slow.vo
VGA\TASK_1\simulation\modelsim\TOP_8_1200mv_0c_v_slow.sdo
VGA\TASK_1\simulation\modelsim\TOP_8_1200mv_85c_slow.vo
VGA\TASK_1\simulation\modelsim\TOP_8_1200mv_85c_v_slow.sdo
VGA\TASK_1\simulation\modelsim\TOP_min_1200mv_0c_fast.vo
VGA\TASK_1\simulation\modelsim\TOP_min_1200mv_0c_v_fast.sdo
VGA\TASK_1\simulation\modelsim\TOP_modelsim.xrf
VGA\TASK_1\simulation\modelsim\TOP_run_msim_rtl_verilog.do
VGA\TASK_1\simulation\modelsim\TOP_v.sdo
VGA\TASK_1\sync_module.v
VGA\TASK_1\sync_module.v.bak
VGA\TASK_1\TOP.qpf
VGA\TASK_1\TOP.qsf
VGA\TASK_1\TOP.qws
VGA\TASK_1\TOP.v
VGA\TASK_1\TOP.v.bak
VGA\TASK_1\TOP_nativelink_simulation.rpt
VGA\TASK_1\vga_control_module.v
VGA\TASK_1\vga_control_module.v.bak
VGA\TASK_2\db\.cmp.kpt
VGA\TASK_2\db\logic_util_heursitic.dat
VGA\TASK_2\db\PLL_altpll.v
VGA\TASK_2\db\prev_cmp_TOP.qmsg
VGA\TASK_2\db\TOP.asm.qmsg
VGA\TASK_2\db\TOP.asm.rdb
VGA\TASK_2\db\TOP.asm_labs.ddb
VGA\TASK_2\db\TOP.cbx.xml
VGA\TASK_2\db\TOP.cmp.bpm
VGA\TASK_2\db\TOP.cmp.cdb
VGA\TASK_2\db\TOP.cmp.hdb
VGA\TASK_2\db\TOP.cmp.idb
VGA\TASK_2\db\TOP.cmp.logdb
VGA\TASK_2\db\TOP.cmp.rdb

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