Arithmetic logical arithmetic units are written in Verilog

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lab2\db\alu.routing.rdb
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lab2\incremental_db\compiled_partitions\alu.root_partition.map.hbdb.cdb
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lab2\incremental_db\compiled_partitions\alu.root_partition.map.hbdb.sig
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lab2\output_files\alu.asm.rpt
lab2\output_files\alu.done
lab2\output_files\alu.fit.rpt
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lab2\output_files\alu.sta.rpt
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lab2\incremental_db\compiled_partitions
lab2\db
lab2\incremental_db
lab2\output_files
lab2

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