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  • Category : VHDL-FPGA-Verilog
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  • Update : 2017-09-21
  • Size : 27kb
  • Downloaded :0次
  • Author :cadet******
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Booth algorithm shift multiply Verilog
Packet file list
(Preview for download)
lab3\booth.qpf
lab3\booth.qsf
lab3\booth.qws
lab3\booth.v
lab3\booth.v.bak
lab3\db\booth.cbx.xml
lab3\db\booth.cmp.rdb
lab3\db\booth.db_info
lab3\db\booth.hif
lab3\db\booth.ipinfo
lab3\db\booth.map.qmsg
lab3\db\booth.map.rdb
lab3\db\booth.map_bb.hdb
lab3\db\booth.pti_db_list.ddb
lab3\db\booth.sld_design_entry.sci
lab3\db\booth.smart_action.txt
lab3\db\booth.tis_db_list.ddb
lab3\db\logic_util_heursitic.dat
lab3\db\prev_cmp_booth.qmsg
lab3\output_files\booth.flow.rpt
lab3\output_files\booth.map.rpt
lab3\output_files\booth.map.summary
lab3\db
lab3\output_files
lab3
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