Finite state machine, FSM, two sections, verilog

fsm\db\fsm.cbx.xml
fsm\db\fsm.cmp.rdb
fsm\db\fsm.db_info
fsm\db\fsm.ipinfo
fsm\db\fsm.map.qmsg
fsm\db\fsm.map.rdb
fsm\db\fsm.map_bb.hdb
fsm\db\fsm.pti_db_list.ddb
fsm\db\fsm.sld_design_entry.sci
fsm\db\fsm.smart_action.txt
fsm\db\fsm.tis_db_list.ddb
fsm\db\logic_util_heursitic.dat
fsm\db\prev_cmp_fsm.qmsg
fsm\fsm.qpf
fsm\fsm.qsf
fsm\fsm.qws
fsm\fsm.v
fsm\fsm.v.bak
fsm\output_files\fsm.flow.rpt
fsm\output_files\fsm.map.rpt
fsm\output_files\fsm.map.summary
fsm\db
fsm\output_files
fsm

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