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prj_ex_4

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2017-09-21
  • Size : 55kb
  • Downloaded :0次
  • Author :宇宇***
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
The detailed analysis of the shift register, through concrete simulation and optimization, found that the code was fully available
Packet file list
(Preview for download)
design\ex_shift_reg.v
sim\data.txt
sim\ex_shift_reg.cr.mti
sim\ex_shift_reg.mpf
sim\lib\work\@_opt\_lib.qdb
sim\lib\work\@_opt\_lib.qdx
sim\lib\work\@_opt\_lib1_0.qdb
sim\lib\work\@_opt\_lib1_0.qpg
sim\lib\work\@_opt\_lib2_0.qdb
sim\lib\work\@_opt\_lib2_0.qdx
sim\lib\work\@_opt\_lib2_0.qpg
sim\lib\work\@_opt\_lib3_0.qdb
sim\lib\work\@_opt\_lib3_0.qdx
sim\lib\work\@_opt\_lib3_0.qpg
sim\lib\work\_info
sim\lib\work\_lib.qdb
sim\lib\work\_lib1_0.qdb
sim\lib\work\_lib1_0.qpg
sim\lib\work\_vmake
sim\lib\_info
sim\run.do
sim\tb_ex_shift_reg.v
sim\vsim.wlf
sim\work\_info
sim\lib\work\@_opt
sim\lib\work
sim\lib
sim\work
design
sim
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