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prj_ex_5

  • Category : VHDL-FPGA-Verilog
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  • Update : 2017-09-21
  • Size : 5.67mb
  • Downloaded :0次
  • Author :宇宇***
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
The automated simulation platform is built using code, and after specific simulation and optimization, it is found that the code is fully available
Packet file list
(Preview for download)
sim\altera_lib\altera_mf.v
sim\altera_lib\altera_primitives.v
sim\altera_lib\cycloneive_atoms.v
sim\ex_mealy.cr.mti
sim\ex_mealy.mpf
sim\ex_mealy_v.sdo
sim\lib\altera_lib\_info
sim\lib\altera_lib\_lib.qdb
sim\lib\altera_lib\_lib1_0.qdb
sim\lib\altera_lib\_lib1_0.qpg
sim\lib\altera_lib\_lib1_1.qdb
sim\lib\altera_lib\_lib1_1.qpg
sim\lib\altera_lib\_vmake
sim\lib\design\_info
sim\lib\design\_lib.qdb
sim\lib\design\_lib1_0.qdb
sim\lib\design\_lib1_0.qpg
sim\lib\design\_vmake
sim\lib\work_a\@_opt\_lib.qdb
sim\lib\work_a\@_opt\_lib.qdx
sim\lib\work_a\@_opt\_lib1_0.qdb
sim\lib\work_a\@_opt\_lib1_0.qpg
sim\lib\work_a\@_opt\_lib2_0.qdb
sim\lib\work_a\@_opt\_lib2_0.qdx
sim\lib\work_a\@_opt\_lib2_0.qpg
sim\lib\work_a\@_opt\_lib3_0.qdb
sim\lib\work_a\@_opt\_lib3_0.qdx
sim\lib\work_a\@_opt\_lib3_0.qpg
sim\lib\work_a\_info
sim\lib\work_a\_lib.qdb
sim\lib\work_a\_lib.qdx
sim\lib\work_a\_lib1_0.qdb
sim\lib\work_a\_lib1_0.qpg
sim\lib\work_a\_lib2_0.qdb
sim\lib\work_a\_lib2_0.qdx
sim\lib\work_a\_lib2_0.qpg
sim\lib\work_a\_vmake
sim\lib\_info
sim\run.do
sim\tb_mealy.v
sim\vsim.wlf
sim\work\_info
design\ex_mealy.vo
design\mealy.v
document\FSM状态迁移图.pdf
document\FSM状态迁移图.vsdx
document\Modelsim 自动化仿真平台搭建.pptx
document\状态机描述风格与技巧.ppt
quartus_prj\db\.cmp.kpt
quartus_prj\db\ex_mealy.cbx.xml
quartus_prj\db\ex_mealy.cmp.bpm
quartus_prj\db\ex_mealy.cmp.cdb
quartus_prj\db\ex_mealy.cmp.hdb
quartus_prj\db\ex_mealy.cmp.idb
quartus_prj\db\ex_mealy.cmp.logdb
quartus_prj\db\ex_mealy.cmp.rdb
quartus_prj\db\ex_mealy.cmp_merge.kpt
quartus_prj\db\ex_mealy.cycloneive_io_sim_cache.45um_ff_1200mv_n40c_fast.hsd
quartus_prj\db\ex_mealy.cycloneive_io_sim_cache.45um_ii_1200mv_125c_slow.hsd
quartus_prj\db\ex_mealy.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
quartus_prj\db\ex_mealy.db_info
quartus_prj\db\ex_mealy.eda.qmsg
quartus_prj\db\ex_mealy.fit.qmsg
quartus_prj\db\ex_mealy.hier_info
quartus_prj\db\ex_mealy.hif
quartus_prj\db\ex_mealy.ipinfo
quartus_prj\db\ex_mealy.lpc.html
quartus_prj\db\ex_mealy.lpc.rdb
quartus_prj\db\ex_mealy.lpc.txt
quartus_prj\db\ex_mealy.map.ammdb
quartus_prj\db\ex_mealy.map.bpm
quartus_prj\db\ex_mealy.map.cdb
quartus_prj\db\ex_mealy.map.hdb
quartus_prj\db\ex_mealy.map.kpt
quartus_prj\db\ex_mealy.map.logdb
quartus_prj\db\ex_mealy.map.qmsg
quartus_prj\db\ex_mealy.map.rdb
quartus_prj\db\ex_mealy.map_bb.cdb
quartus_prj\db\ex_mealy.map_bb.hdb
quartus_prj\db\ex_mealy.map_bb.logdb
quartus_prj\db\ex_mealy.pre_map.hdb
quartus_prj\db\ex_mealy.pti_db_list.ddb
quartus_prj\db\ex_mealy.root_partition.map.reg_db.cdb
quartus_prj\db\ex_mealy.routing.rdb
quartus_prj\db\ex_mealy.rtlv.hdb
quartus_prj\db\ex_mealy.rtlv_sg.cdb
quartus_prj\db\ex_mealy.rtlv_sg_swap.cdb
quartus_prj\db\ex_mealy.sgdiff.cdb
quartus_prj\db\ex_mealy.sgdiff.hdb
quartus_prj\db\ex_mealy.sld_design_entry.sci
quartus_prj\db\ex_mealy.sld_design_entry_dsc.sci
quartus_prj\db\ex_mealy.smart_action.txt
quartus_prj\db\ex_mealy.smp_dump.txt
quartus_prj\db\ex_mealy.tiscmp.fastest_slow_1200mv_85c.ddb
quartus_prj\db\ex_mealy.tiscmp.fast_1200mv_n40c.ddb
quartus_prj\db\ex_mealy.tiscmp.slow_1200mv_125c.ddb
quartus_prj\db\ex_mealy.tis_db_list.ddb
quartus_prj\db\ex_mealy.tmw_info
quartus_prj\db\ex_mealy.vpr.ammdb
quartus_prj\db\logic_util_heursitic.dat
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