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FourToOneMux

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2017-09-24
  • Size : 27kb
  • Downloaded :0次
  • Author :Mo***
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
this is Implementation of 4 to 1 Multiplexer in verilog language for embedded design systems
Packet file list
(Preview for download)
lab#3
lab#3\lab_3.cr.mti
lab#3\lab_3.mpf
lab#3\task_3.v
lab#3\test_task.v
lab#3\vsim.wlf
lab#3\work
lab#3\work\@a@l@u
lab#3\work\@a@l@u\verilog.asm
lab#3\work\@a@l@u\_primary.dat
lab#3\work\@a@l@u\_primary.vhd
lab#3\work\@a@l@u_@test
lab#3\work\@a@l@u_@test\verilog.asm
lab#3\work\@a@l@u_@test\_primary.dat
lab#3\work\@a@l@u_@test\_primary.vhd
lab#3\work\counter4bit
lab#3\work\counter4bit\verilog.asm
lab#3\work\counter4bit\_primary.dat
lab#3\work\counter4bit\_primary.vhd
lab#3\work\mux8to1
lab#3\work\mux8to1\verilog.asm
lab#3\work\mux8to1\_primary.dat
lab#3\work\mux8to1\_primary.vhd
lab#3\work\test_8to1
lab#3\work\test_8to1\verilog.asm
lab#3\work\test_8to1\_primary.dat
lab#3\work\test_8to1\_primary.vhd
lab#3\work\test_counter
lab#3\work\test_counter\verilog.asm
lab#3\work\test_counter\_primary.dat
lab#3\work\test_counter\_primary.vhd
lab#3\work\_info
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