VHDL generating of trig down signal microsemi project

test60_TRIGD\component
test60_TRIGD\component\work
test60_TRIGD\component\work\tb_top
test60_TRIGD\component\work\tb_top\tb_top.cxf
test60_TRIGD\component\work\tb_top\tb_top.sdb
test60_TRIGD\component\work\tb_top\tb_top.vhd
test60_TRIGD\component\work\tb_top\tb_top_manifest.txt
test60_TRIGD\constraint
test60_TRIGD\coreconsole
test60_TRIGD\designer
test60_TRIGD\designer\impl1
test60_TRIGD\designer\impl1\designer_synth_check.log
test60_TRIGD\designer\impl1\simulation
test60_TRIGD\designer\impl1\TRIGD.ide_des
test60_TRIGD\designer\impl1\TRIGD.tcl
test60_TRIGD\hdl
test60_TRIGD\hdl\TRIGD.vhd
test60_TRIGD\simulation
test60_TRIGD\simulation\modelsim.ini
test60_TRIGD\simulation\postsynth
test60_TRIGD\simulation\postsynth\_info
test60_TRIGD\simulation\postsynth\_lib.qdb
test60_TRIGD\simulation\postsynth\_lib1_0.qdb
test60_TRIGD\simulation\postsynth\_lib1_0.qpg
test60_TRIGD\simulation\postsynth\_lib1_0.qtl
test60_TRIGD\simulation\postsynth\_vmake
test60_TRIGD\simulation\run.do
test60_TRIGD\simulation\tb_top_postsynth_simulation.log
test60_TRIGD\simulation\vsim.wlf
test60_TRIGD\smartgen
test60_TRIGD\smartgen\smartgen.aws
test60_TRIGD\smartgen\tb_top_work.ixf
test60_TRIGD\stimulus
test60_TRIGD\stimulus\tb_clk.vhd
test60_TRIGD\synthesis
test60_TRIGD\synthesis\.recordref
test60_TRIGD\synthesis\backup
test60_TRIGD\synthesis\backup\TRIGD.srr
test60_TRIGD\synthesis\coreip
test60_TRIGD\synthesis\dm
test60_TRIGD\synthesis\dm\layer0.xdm
test60_TRIGD\synthesis\run_options.txt
test60_TRIGD\synthesis\scratchproject.prs
test60_TRIGD\synthesis\synlog.tcl
test60_TRIGD\synthesis\synlog
test60_TRIGD\synthesis\synlog\layer0.tlg.rptmap
test60_TRIGD\synthesis\synlog\report
test60_TRIGD\synthesis\synlog\report\TRIGD_compiler_notes.txt
test60_TRIGD\synthesis\synlog\report\TRIGD_compiler_runstatus.xml
test60_TRIGD\synthesis\synlog\report\TRIGD_fpga_mapper_area_report.xml
test60_TRIGD\synthesis\synlog\report\TRIGD_fpga_mapper_combined_clk.rpt
test60_TRIGD\synthesis\synlog\report\TRIGD_fpga_mapper_errors.txt
test60_TRIGD\synthesis\synlog\report\TRIGD_fpga_mapper_notes.txt
test60_TRIGD\synthesis\synlog\report\TRIGD_fpga_mapper_opt_report.xml
test60_TRIGD\synthesis\synlog\report\TRIGD_fpga_mapper_resourceusage.rpt
test60_TRIGD\synthesis\synlog\report\TRIGD_fpga_mapper_runstatus.xml
test60_TRIGD\synthesis\synlog\report\TRIGD_fpga_mapper_timing_report.xml
test60_TRIGD\synthesis\synlog\report\TRIGD_fpga_mapper_warnings.txt
test60_TRIGD\synthesis\synlog\report\TRIGD_premap_errors.txt
test60_TRIGD\synthesis\synlog\report\TRIGD_premap_notes.txt
test60_TRIGD\synthesis\synlog\report\TRIGD_premap_runstatus.xml
test60_TRIGD\synthesis\synlog\report\TRIGD_premap_warnings.txt
test60_TRIGD\synthesis\synlog\syntax_constraint_check.rpt.rptmap
test60_TRIGD\synthesis\synlog\TRIGD_compiler.srr
test60_TRIGD\synthesis\synlog\TRIGD_compiler.srr.rptmap
test60_TRIGD\synthesis\synlog\TRIGD_fpga_mapper.srr
test60_TRIGD\synthesis\synlog\TRIGD_fpga_mapper.szr
test60_TRIGD\synthesis\synlog\TRIGD_fpga_mapper.xck
test60_TRIGD\synthesis\synlog\TRIGD_multi_srs_gen.srr
test60_TRIGD\synthesis\synlog\TRIGD_premap.srr
test60_TRIGD\synthesis\synlog\TRIGD_premap.szr
test60_TRIGD\synthesis\synplify.log
test60_TRIGD\synthesis\syntmp
test60_TRIGD\synthesis\syntmp\closed.png
test60_TRIGD\synthesis\syntmp\cmdrec_compiler.log
test60_TRIGD\synthesis\syntmp\cmdrec_fpga_mapper.log
test60_TRIGD\synthesis\syntmp\cmdrec_multi_srs_gen.log
test60_TRIGD\synthesis\syntmp\cmdrec_premap.log
test60_TRIGD\synthesis\syntmp\open.png
test60_TRIGD\synthesis\syntmp\run_option.xml
test60_TRIGD\synthesis\syntmp\statusReport.html
test60_TRIGD\synthesis\syntmp\TRIGD.plg
test60_TRIGD\synthesis\syntmp\TRIGD_srr.htm
test60_TRIGD\synthesis\syntmp\TRIGD_toc.htm
test60_TRIGD\synthesis\synwork
test60_TRIGD\synthesis\synwork\.cckTransfer
test60_TRIGD\synthesis\synwork\_mh_info
test60_TRIGD\synthesis\synwork\layer0.fdep
test60_TRIGD\synthesis\synwork\layer0.fdeporig
test60_TRIGD\synthesis\synwork\layer0.srs
test60_TRIGD\synthesis\synwork\layer0.tlg
test60_TRIGD\synthesis\synwork\TRIGD_comp.fdep
test60_TRIGD\synthesis\synwork\TRIGD_comp.srs
test60_TRIGD\synthesis\synwork\TRIGD_m.srm
test60_TRIGD\synthesis\synwork\TRIGD_m_srm
test60_TRIGD\synthesis\synwork\TRIGD_m_srm\fileinfo.srm
test60_TRIGD\synthesis\synwork\TRIGD_mult.srs
test60_TRIGD\synthesis\synwork\TRIGD_mult_srs
test60_TRIGD\synthesis\synwork\TRIGD_mult_srs\fileinfo.srs
test60_TRIGD\synthesis\synwork\TRIGD_mult_srs\skeleton.srs

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