RS232 communication protocol Verilog program. After debugging can be used

RS232_verilog1\AD420_TX.v.bak
RS232_verilog1\db\logic_util_heursitic.dat
RS232_verilog1\db\prev_cmp_uart_rx.qmsg
RS232_verilog1\db\uart_rx.asm.qmsg
RS232_verilog1\db\uart_rx.asm.rdb
RS232_verilog1\db\uart_rx.cbx.xml
RS232_verilog1\db\uart_rx.cmp.bpm
RS232_verilog1\db\uart_rx.cmp.cdb
RS232_verilog1\db\uart_rx.cmp.hdb
RS232_verilog1\db\uart_rx.cmp.idb
RS232_verilog1\db\uart_rx.cmp.kpt
RS232_verilog1\db\uart_rx.cmp.logdb
RS232_verilog1\db\uart_rx.cmp.rdb
RS232_verilog1\db\uart_rx.cmp0.ddb
RS232_verilog1\db\uart_rx.cmp_merge.kpt
RS232_verilog1\db\uart_rx.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
RS232_verilog1\db\uart_rx.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd
RS232_verilog1\db\uart_rx.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
RS232_verilog1\db\uart_rx.db_info
RS232_verilog1\db\uart_rx.eda.qmsg
RS232_verilog1\db\uart_rx.fit.qmsg
RS232_verilog1\db\uart_rx.hier_info
RS232_verilog1\db\uart_rx.hif
RS232_verilog1\db\uart_rx.ipinfo
RS232_verilog1\db\uart_rx.lpc.html
RS232_verilog1\db\uart_rx.lpc.rdb
RS232_verilog1\db\uart_rx.lpc.txt
RS232_verilog1\db\uart_rx.map.ammdb
RS232_verilog1\db\uart_rx.map.bpm
RS232_verilog1\db\uart_rx.map.cdb
RS232_verilog1\db\uart_rx.map.hdb
RS232_verilog1\db\uart_rx.map.kpt
RS232_verilog1\db\uart_rx.map.logdb
RS232_verilog1\db\uart_rx.map.qmsg
RS232_verilog1\db\uart_rx.map.rdb
RS232_verilog1\db\uart_rx.map_bb.cdb
RS232_verilog1\db\uart_rx.map_bb.hdb
RS232_verilog1\db\uart_rx.map_bb.logdb
RS232_verilog1\db\uart_rx.pplq.rdb
RS232_verilog1\db\uart_rx.pre_map.hdb
RS232_verilog1\db\uart_rx.pti_db_list.ddb
RS232_verilog1\db\uart_rx.root_partition.map.reg_db.cdb
RS232_verilog1\db\uart_rx.routing.rdb
RS232_verilog1\db\uart_rx.rpp.qmsg
RS232_verilog1\db\uart_rx.rtlv.hdb
RS232_verilog1\db\uart_rx.rtlv_sg.cdb
RS232_verilog1\db\uart_rx.rtlv_sg_swap.cdb
RS232_verilog1\db\uart_rx.sgate.rvd
RS232_verilog1\db\uart_rx.sgate_sm.rvd
RS232_verilog1\db\uart_rx.sgdiff.cdb
RS232_verilog1\db\uart_rx.sgdiff.hdb
RS232_verilog1\db\uart_rx.sld_design_entry.sci
RS232_verilog1\db\uart_rx.sld_design_entry_dsc.sci
RS232_verilog1\db\uart_rx.smart_action.txt
RS232_verilog1\db\uart_rx.sta.qmsg
RS232_verilog1\db\uart_rx.sta.rdb
RS232_verilog1\db\uart_rx.sta_cmp.8_slow.tdb
RS232_verilog1\db\uart_rx.stingray_io_sim_cache.99um_ff_1200mv_0c_fast.hsd
RS232_verilog1\db\uart_rx.stingray_io_sim_cache.99um_tt_1200mv_0c_slow.hsd
RS232_verilog1\db\uart_rx.stingray_io_sim_cache.99um_tt_1200mv_85c_slow.hsd
RS232_verilog1\db\uart_rx.syn_hier_info
RS232_verilog1\db\uart_rx.tiscmp.fastest_slow_1200mv_0c.ddb
RS232_verilog1\db\uart_rx.tiscmp.fastest_slow_1200mv_85c.ddb
RS232_verilog1\db\uart_rx.tis_db_list.ddb
RS232_verilog1\db\uart_rx.vpr.ammdb
RS232_verilog1\incremental_db\compiled_partitions\uart_rx.db_info
RS232_verilog1\incremental_db\compiled_partitions\uart_rx.root_partition.cmp.ammdb
RS232_verilog1\incremental_db\compiled_partitions\uart_rx.root_partition.cmp.cdb
RS232_verilog1\incremental_db\compiled_partitions\uart_rx.root_partition.cmp.dfp
RS232_verilog1\incremental_db\compiled_partitions\uart_rx.root_partition.cmp.hdb
RS232_verilog1\incremental_db\compiled_partitions\uart_rx.root_partition.cmp.kpt
RS232_verilog1\incremental_db\compiled_partitions\uart_rx.root_partition.cmp.logdb
RS232_verilog1\incremental_db\compiled_partitions\uart_rx.root_partition.cmp.rcfdb
RS232_verilog1\incremental_db\compiled_partitions\uart_rx.root_partition.map.cdb
RS232_verilog1\incremental_db\compiled_partitions\uart_rx.root_partition.map.dpi
RS232_verilog1\incremental_db\compiled_partitions\uart_rx.root_partition.map.hbdb.cdb
RS232_verilog1\incremental_db\compiled_partitions\uart_rx.root_partition.map.hbdb.hb_info
RS232_verilog1\incremental_db\compiled_partitions\uart_rx.root_partition.map.hbdb.hdb
RS232_verilog1\incremental_db\compiled_partitions\uart_rx.root_partition.map.hbdb.sig
RS232_verilog1\incremental_db\compiled_partitions\uart_rx.root_partition.map.hdb
RS232_verilog1\incremental_db\compiled_partitions\uart_rx.root_partition.map.kpt
RS232_verilog1\incremental_db\README
RS232_verilog1\mytop.v
RS232_verilog1\mytop.v.bak
RS232_verilog1\my_uart.v
RS232_verilog1\my_uart.v.bak
RS232_verilog1\my_uart_1.v
RS232_verilog1\my_uart_1.v.bak
RS232_verilog1\output_files\AD420.done
RS232_verilog1\output_files\uart_rx.asm.rpt
RS232_verilog1\output_files\uart_rx.cdf
RS232_verilog1\output_files\uart_rx.done
RS232_verilog1\output_files\uart_rx.eda.rpt
RS232_verilog1\output_files\uart_rx.fit.rpt
RS232_verilog1\output_files\uart_rx.fit.smsg
RS232_verilog1\output_files\uart_rx.fit.summary
RS232_verilog1\output_files\uart_rx.flow.rpt
RS232_verilog1\output_files\uart_rx.jdi
RS232_verilog1\output_files\uart_rx.map.rpt
RS232_verilog1\output_files\uart_rx.map.summary

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