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DE2-115_Basic_Computer
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Category :
VHDL-FPGA-Verilog
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Update : 2017-10-06
Size : 677kb
Downloaded :0次
Author :
chun****
About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
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BASIC COMPUTER FOR JTAG_UART
Packet file list
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DE2-115_Basic_Computer
DE2-115_Basic_Computer\app_software
DE2-115_Basic_Computer\app_software\JTAG_UART_C
DE2-115_Basic_Computer\app_software\JTAG_UART_C\JTAG_UART.c
DE2-115_Basic_Computer\app_software\JTAG_UART_C\JTAG_UART_C.ncf
DE2-115_Basic_Computer\app_software\JTAG_UART_s
DE2-115_Basic_Computer\app_software\JTAG_UART_s\JTAG_UART.s
DE2-115_Basic_Computer\app_software\JTAG_UART_s\JTAG_UART_s.ncf
DE2-115_Basic_Computer\app_software\getting_started_C
DE2-115_Basic_Computer\app_software\getting_started_C\getting_started.c
DE2-115_Basic_Computer\app_software\getting_started_C\getting_started_C.ncf
DE2-115_Basic_Computer\app_software\getting_started_s
DE2-115_Basic_Computer\app_software\getting_started_s\getting_started.s
DE2-115_Basic_Computer\app_software\getting_started_s\getting_started_s.ncf
DE2-115_Basic_Computer\app_software\interrupt_example_C
DE2-115_Basic_Computer\app_software\interrupt_example_C\exception_handler.c
DE2-115_Basic_Computer\app_software\interrupt_example_C\interrupt_example.c
DE2-115_Basic_Computer\app_software\interrupt_example_C\interrupt_example_C.ncf
DE2-115_Basic_Computer\app_software\interrupt_example_C\interval_timer_ISR.c
DE2-115_Basic_Computer\app_software\interrupt_example_C\key_codes.h
DE2-115_Basic_Computer\app_software\interrupt_example_C\nios2_ctrl_reg_macros.h
DE2-115_Basic_Computer\app_software\interrupt_example_C\pushbutton_ISR.c
DE2-115_Basic_Computer\app_software\interrupt_example_s
DE2-115_Basic_Computer\app_software\interrupt_example_s\exception_handler.s
DE2-115_Basic_Computer\app_software\interrupt_example_s\interrupt_example.s
DE2-115_Basic_Computer\app_software\interrupt_example_s\interrupt_example_s.ncf
DE2-115_Basic_Computer\app_software\interrupt_example_s\interval_timer.s
DE2-115_Basic_Computer\app_software\interrupt_example_s\key_codes.s
DE2-115_Basic_Computer\app_software\interrupt_example_s\pushbutton_ISR.s
DE2-115_Basic_Computer\app_software\test_Basic_Computer_C
DE2-115_Basic_Computer\app_software\test_Basic_Computer_C\address_map.h
DE2-115_Basic_Computer\app_software\test_Basic_Computer_C\exceptions.c
DE2-115_Basic_Computer\app_software\test_Basic_Computer_C\interval_timer.c
DE2-115_Basic_Computer\app_software\test_Basic_Computer_C\nios2_ctrl_reg_macros.h
DE2-115_Basic_Computer\app_software\test_Basic_Computer_C\pushbutton.c
DE2-115_Basic_Computer\app_software\test_Basic_Computer_C\test_Basic_Computer.c
DE2-115_Basic_Computer\app_software\test_Basic_Computer_C\test_Basic_Computer_C.ncf
DE2-115_Basic_Computer\app_software\test_Basic_Computer_s
DE2-115_Basic_Computer\app_software\test_Basic_Computer_s\address_map.s
DE2-115_Basic_Computer\app_software\test_Basic_Computer_s\exceptions.s
DE2-115_Basic_Computer\app_software\test_Basic_Computer_s\interval_timer.s
DE2-115_Basic_Computer\app_software\test_Basic_Computer_s\pushbutton.s
DE2-115_Basic_Computer\app_software\test_Basic_Computer_s\test_Basic_Computer.s
DE2-115_Basic_Computer\app_software\test_Basic_Computer_s\test_Basic_Computer_s.ncf
DE2-115_Basic_Computer\doc
DE2-115_Basic_Computer\doc\DE2-115_Basic_Computer.pdf
DE2-115_Basic_Computer\verilog
DE2-115_Basic_Computer\verilog\.sopc_builder
DE2-115_Basic_Computer\verilog\.sopc_builder\filters.xml
DE2-115_Basic_Computer\verilog\.sopc_builder\install2.ptf
DE2-115_Basic_Computer\verilog\.sopc_builder\preferences.xml
DE2-115_Basic_Computer\verilog\CPU.sdc
DE2-115_Basic_Computer\verilog\CPU.v
DE2-115_Basic_Computer\verilog\CPU_jtag_debug_module_sysclk.v
DE2-115_Basic_Computer\verilog\CPU_jtag_debug_module_tck.v
DE2-115_Basic_Computer\verilog\CPU_jtag_debug_module_wrapper.v
DE2-115_Basic_Computer\verilog\CPU_oci_test_bench.v
DE2-115_Basic_Computer\verilog\CPU_ociram_default_contents.mif
DE2-115_Basic_Computer\verilog\CPU_rf_ram.mif
DE2-115_Basic_Computer\verilog\CPU_test_bench.v
DE2-115_Basic_Computer\verilog\DE2_115_Basic_Computer.qpf
DE2-115_Basic_Computer\verilog\DE2_115_Basic_Computer.qsf
DE2-115_Basic_Computer\verilog\DE2_115_Basic_Computer.sof
DE2-115_Basic_Computer\verilog\DE2_115_Basic_Computer.v
DE2-115_Basic_Computer\verilog\DE2_115_Basic_Computer_assignment_defaults.qdf
DE2-115_Basic_Computer\verilog\Expansion_JP5.v
DE2-115_Basic_Computer\verilog\Green_LEDs.v
DE2-115_Basic_Computer\verilog\HEX3_HEX0.v
DE2-115_Basic_Computer\verilog\HEX7_HEX4.v
DE2-115_Basic_Computer\verilog\Interval_Timer.v
DE2-115_Basic_Computer\verilog\JTAG_UART.v
DE2-115_Basic_Computer\verilog\Onchip_memory.hex
DE2-115_Basic_Computer\verilog\Onchip_memory.v
DE2-115_Basic_Computer\verilog\Pushbuttons.v
DE2-115_Basic_Computer\verilog\Red_LEDs.v
DE2-115_Basic_Computer\verilog\SDRAM.v
DE2-115_Basic_Computer\verilog\SRAM.v
DE2-115_Basic_Computer\verilog\Serial_Port.v
DE2-115_Basic_Computer\verilog\Slider_Switches.v
DE2-115_Basic_Computer\verilog\altera_up_rs232_counters.v
DE2-115_Basic_Computer\verilog\altera_up_rs232_in_deserializer.v
DE2-115_Basic_Computer\verilog\altera_up_rs232_out_serializer.v
DE2-115_Basic_Computer\verilog\altera_up_sync_fifo.v
DE2-115_Basic_Computer\verilog\db
DE2-115_Basic_Computer\verilog\db\DE2_115_Basic_Computer.db_info
DE2-115_Basic_Computer\verilog\db\DE2_115_Basic_Computer.sld_design_entry.sci
DE2-115_Basic_Computer\verilog\db\sopcb_tb2_nios_system.xml
DE2-115_Basic_Computer\verilog\greybox_tmp
DE2-115_Basic_Computer\verilog\greybox_tmp\cbx_args.txt
DE2-115_Basic_Computer\verilog\nios_system.html
DE2-115_Basic_Computer\verilog\nios_system.ptf
DE2-115_Basic_Computer\verilog\nios_system.qip
DE2-115_Basic_Computer\verilog\nios_system.sopc
DE2-115_Basic_Computer\verilog\nios_system.sopcinfo
DE2-115_Basic_Computer\verilog\nios_system.v
DE2-115_Basic_Computer\verilog\sdram_pll.qip
DE2-115_Basic_Computer\verilog\sdram_pll.v
DE2-115_Basic_Computer\verilog\sopc_add_qip_file.tcl
DE2-115_Basic_Computer\verilog\sopc_builder_log.txt
DE2-115_Basic_Computer\verilog\sysid.v
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