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  • Category : VHDL-FPGA-Verilog
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  • Update : 2017-10-16
  • Size : 3.02mb
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  • Author :qing *****
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Introduction - If you have any usage issues, please Google them yourself
Using the counter to design the delay function, through the flashing of four LED lights, we can observe the delay time directly, FPGA device cyclone IV LCMXO2-1200HC-4TG144CR1, and make the simple path diagram on the demo board
Packet file list
(Preview for download)
led\db\led.asm.qmsg
led\db\led.asm.rdb
led\db\led.asm_labs.ddb
led\db\led.cbx.xml
led\db\led.cmp.bpm
led\db\led.cmp.cdb
led\db\led.cmp.hdb
led\db\led.cmp.idb
led\db\led.cmp.kpt
led\db\led.cmp.logdb
led\db\led.cmp.rdb
led\db\led.cmp_merge.kpt
led\db\led.cycloneive_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
led\db\led.cycloneive_io_sim_cache.31um_ss_1200mv_0c_slow.hsd
led\db\led.cycloneive_io_sim_cache.31um_ss_1200mv_85c_slow.hsd
led\db\led.db_info
led\db\led.eda.qmsg
led\db\led.fit.qmsg
led\db\led.hier_info
led\db\led.hif
led\db\led.ipinfo
led\db\led.lpc.html
led\db\led.lpc.rdb
led\db\led.lpc.txt
led\db\led.map.ammdb
led\db\led.map.bpm
led\db\led.map.cdb
led\db\led.map.hdb
led\db\led.map.kpt
led\db\led.map.logdb
led\db\led.map.qmsg
led\db\led.map.rdb
led\db\led.map_bb.cdb
led\db\led.map_bb.hdb
led\db\led.map_bb.logdb
led\db\led.pre_map.hdb
led\db\led.pti_db_list.ddb
led\db\led.root_partition.map.reg_db.cdb
led\db\led.routing.rdb
led\db\led.rtlv.hdb
led\db\led.rtlv_sg.cdb
led\db\led.rtlv_sg_swap.cdb
led\db\led.sgdiff.cdb
led\db\led.sgdiff.hdb
led\db\led.sld_design_entry.sci
led\db\led.sld_design_entry_dsc.sci
led\db\led.smart_action.txt
led\db\led.sta.qmsg
led\db\led.sta.rdb
led\db\led.sta_cmp.8_slow_1200mv_85c.tdb
led\db\led.syn_hier_info
led\db\led.tiscmp.fastest_slow_1200mv_0c.ddb
led\db\led.tiscmp.fastest_slow_1200mv_85c.ddb
led\db\led.tiscmp.fast_1200mv_0c.ddb
led\db\led.tiscmp.slow_1200mv_0c.ddb
led\db\led.tiscmp.slow_1200mv_85c.ddb
led\db\led.tis_db_list.ddb
led\db\led.tmw_info
led\db\led.vpr.ammdb
led\db\led_qsim.cbx.xml
led\db\led_qsim.db_info
led\db\led_qsim.eds_overflow
led\db\led_qsim.fnsim.cdb
led\db\led_qsim.fnsim.hdb
led\db\led_qsim.fnsim.qmsg
led\db\led_qsim.hier_info
led\db\led_qsim.lpc.html
led\db\led_qsim.lpc.rdb
led\db\led_qsim.lpc.txt
led\db\led_qsim.sim.hdb
led\db\led_qsim.sim.qmsg
led\db\led_qsim.sim.rdb
led\db\led_qsim.sim.vwf
led\db\led_qsim.simfam
led\db\led_qsim.sld_design_entry_dsc.sci
led\db\led_qsim.smart_action.txt
led\db\logic_util_heursitic.dat
led\db\prev_cmp_led.qmsg
led\incremental_db\compiled_partitions\led.db_info
led\incremental_db\compiled_partitions\led.root_partition.cmp.ammdb
led\incremental_db\compiled_partitions\led.root_partition.cmp.cdb
led\incremental_db\compiled_partitions\led.root_partition.cmp.dfp
led\incremental_db\compiled_partitions\led.root_partition.cmp.hdb
led\incremental_db\compiled_partitions\led.root_partition.cmp.kpt
led\incremental_db\compiled_partitions\led.root_partition.cmp.logdb
led\incremental_db\compiled_partitions\led.root_partition.cmp.rcfdb
led\incremental_db\compiled_partitions\led.root_partition.map.cdb
led\incremental_db\compiled_partitions\led.root_partition.map.dpi
led\incremental_db\compiled_partitions\led.root_partition.map.hbdb.cdb
led\incremental_db\compiled_partitions\led.root_partition.map.hbdb.hb_info
led\incremental_db\compiled_partitions\led.root_partition.map.hbdb.hdb
led\incremental_db\compiled_partitions\led.root_partition.map.hbdb.sig
led\incremental_db\compiled_partitions\led.root_partition.map.hdb
led\incremental_db\compiled_partitions\led.root_partition.map.kpt
led\incremental_db\compiled_partitions\led_qsim.db_info
led\incremental_db\README
led\led.bsf
led\led.qpf
led\led.qsf
led\led.qws
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