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MVA15_Japan_Harris_FPGA_Vivado_source

  • Category : VHDL-FPGA-Verilog
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  • Update : 2017-10-22
  • Size : 19kb
  • Downloaded :0次
  • Author :sudoh*****
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Introduction - If you have any usage issues, please Google them yourself
Tak Lon Chao, Kin Hong Wong, "An efficient FPGA implementation of the Harris Corner feature detector", The 14th IAPR Conference on Machine Vision Applications (MVA 2015), MIRAIKAN: National Museum of Emerging Science and Innovation in Tokyo, Japan, 18-22 May 2015 video1 video2 Code:in VHDL and Verliog running on Zedboard
Packet file list
(Preview for download)
MVA15_Japan_Harris_FPGA_Vivado_source
MVA15_Japan_Harris_FPGA_Vivado_source\address_Generator.vhd
MVA15_Japan_Harris_FPGA_Vivado_source\cv_top.v
MVA15_Japan_Harris_FPGA_Vivado_source\debounce.vhd
MVA15_Japan_Harris_FPGA_Vivado_source\frame_buffer.v
MVA15_Japan_Harris_FPGA_Vivado_source\i3c2.vhd
MVA15_Japan_Harris_FPGA_Vivado_source\ov7670_capture.vhd
MVA15_Japan_Harris_FPGA_Vivado_source\ov7670_controller.vhd
MVA15_Japan_Harris_FPGA_Vivado_source\Readme.txt
MVA15_Japan_Harris_FPGA_Vivado_source\RGB.vhd
MVA15_Japan_Harris_FPGA_Vivado_source\top_level.vhd
MVA15_Japan_Harris_FPGA_Vivado_source\vga.vhd
MVA15_Japan_Harris_FPGA_Vivado_source\vga_pll_zedboard.vhd
MVA15_Japan_Harris_FPGA_Vivado_source\zedboard.xdc
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