DDR3 read and write operations,the use of spartan6 platform validation.

ddr3_128\ddr3_128.gise
ddr3_128\ddr3_128.xise
ddr3_128\example_top.bld
ddr3_128\example_top.cmd_log
ddr3_128\example_top.lso
ddr3_128\example_top.ncd
ddr3_128\example_top.ngc
ddr3_128\example_top.ngd
ddr3_128\example_top.ngr
ddr3_128\example_top.par
ddr3_128\example_top.pcf
ddr3_128\example_top.prj
ddr3_128\example_top.stx
ddr3_128\example_top.syr
ddr3_128\example_top.twr
ddr3_128\example_top.twx
ddr3_128\example_top.unroutes
ddr3_128\example_top.xst
ddr3_128\example_top_envsettings.html
ddr3_128\example_top_guide.ncd
ddr3_128\example_top_map.map
ddr3_128\example_top_map.mrp
ddr3_128\example_top_map.ncd
ddr3_128\example_top_map.ngm
ddr3_128\example_top_pad.csv
ddr3_128\example_top_pad.txt
ddr3_128\example_top_summary.html
ddr3_128\example_top_xst.xrpt
ddr3_128\fuse.log
ddr3_128\fuse.xmsgs
ddr3_128\fuseRelaunch.cmd
ddr3_128\ipcore_dir\clk_wiz_v3_6\clk_wiz_v3_6_readme.txt
ddr3_128\ipcore_dir\clk_wiz_v3_6\doc\clk_wiz_v3_6_readme.txt
ddr3_128\ipcore_dir\clk_wiz_v3_6\doc\clk_wiz_v3_6_vinfo.html
ddr3_128\ipcore_dir\clk_wiz_v3_6\doc\pg065_clk_wiz.pdf
ddr3_128\ipcore_dir\clk_wiz_v3_6\example_design\clk_wiz_v3_6_exdes.ucf
ddr3_128\ipcore_dir\clk_wiz_v3_6\example_design\clk_wiz_v3_6_exdes.v
ddr3_128\ipcore_dir\clk_wiz_v3_6\example_design\clk_wiz_v3_6_exdes.xdc
ddr3_128\ipcore_dir\clk_wiz_v3_6\implement\implement.bat
ddr3_128\ipcore_dir\clk_wiz_v3_6\implement\implement.sh
ddr3_128\ipcore_dir\clk_wiz_v3_6\implement\planAhead_ise.bat
ddr3_128\ipcore_dir\clk_wiz_v3_6\implement\planAhead_ise.sh
ddr3_128\ipcore_dir\clk_wiz_v3_6\implement\planAhead_ise.tcl
ddr3_128\ipcore_dir\clk_wiz_v3_6\implement\planAhead_rdn.bat
ddr3_128\ipcore_dir\clk_wiz_v3_6\implement\planAhead_rdn.sh
ddr3_128\ipcore_dir\clk_wiz_v3_6\implement\planAhead_rdn.tcl
ddr3_128\ipcore_dir\clk_wiz_v3_6\implement\xst.prj
ddr3_128\ipcore_dir\clk_wiz_v3_6\implement\xst.scr
ddr3_128\ipcore_dir\clk_wiz_v3_6\simulation\clk_wiz_v3_6_tb.v
ddr3_128\ipcore_dir\clk_wiz_v3_6\simulation\functional\simcmds.tcl
ddr3_128\ipcore_dir\clk_wiz_v3_6\simulation\functional\simulate_isim.bat
ddr3_128\ipcore_dir\clk_wiz_v3_6\simulation\functional\simulate_isim.sh
ddr3_128\ipcore_dir\clk_wiz_v3_6\simulation\functional\simulate_mti.bat
ddr3_128\ipcore_dir\clk_wiz_v3_6\simulation\functional\simulate_mti.do
ddr3_128\ipcore_dir\clk_wiz_v3_6\simulation\functional\simulate_mti.sh
ddr3_128\ipcore_dir\clk_wiz_v3_6\simulation\functional\simulate_ncsim.sh
ddr3_128\ipcore_dir\clk_wiz_v3_6\simulation\functional\simulate_vcs.sh
ddr3_128\ipcore_dir\clk_wiz_v3_6\simulation\functional\ucli_commands.key
ddr3_128\ipcore_dir\clk_wiz_v3_6\simulation\functional\vcs_session.tcl
ddr3_128\ipcore_dir\clk_wiz_v3_6\simulation\functional\wave.do
ddr3_128\ipcore_dir\clk_wiz_v3_6\simulation\functional\wave.sv
ddr3_128\ipcore_dir\clk_wiz_v3_6\simulation\timing\clk_wiz_v3_6_tb.v
ddr3_128\ipcore_dir\clk_wiz_v3_6\simulation\timing\sdf_cmd_file
ddr3_128\ipcore_dir\clk_wiz_v3_6\simulation\timing\simcmds.tcl
ddr3_128\ipcore_dir\clk_wiz_v3_6\simulation\timing\simulate_isim.sh
ddr3_128\ipcore_dir\clk_wiz_v3_6\simulation\timing\simulate_mti.bat
ddr3_128\ipcore_dir\clk_wiz_v3_6\simulation\timing\simulate_mti.do
ddr3_128\ipcore_dir\clk_wiz_v3_6\simulation\timing\simulate_mti.sh
ddr3_128\ipcore_dir\clk_wiz_v3_6\simulation\timing\simulate_ncsim.sh
ddr3_128\ipcore_dir\clk_wiz_v3_6\simulation\timing\simulate_vcs.sh
ddr3_128\ipcore_dir\clk_wiz_v3_6\simulation\timing\ucli_commands.key
ddr3_128\ipcore_dir\clk_wiz_v3_6\simulation\timing\vcs_session.tcl
ddr3_128\ipcore_dir\clk_wiz_v3_6\simulation\timing\wave.do
ddr3_128\ipcore_dir\clk_wiz_v3_6.asy
ddr3_128\ipcore_dir\clk_wiz_v3_6.gise
ddr3_128\ipcore_dir\clk_wiz_v3_6.ncf
ddr3_128\ipcore_dir\clk_wiz_v3_6.ucf
ddr3_128\ipcore_dir\clk_wiz_v3_6.v
ddr3_128\ipcore_dir\clk_wiz_v3_6.veo
ddr3_128\ipcore_dir\clk_wiz_v3_6.xco
ddr3_128\ipcore_dir\clk_wiz_v3_6.xdc
ddr3_128\ipcore_dir\clk_wiz_v3_6.xise
ddr3_128\ipcore_dir\clk_wiz_v3_6_flist.txt
ddr3_128\ipcore_dir\clk_wiz_v3_6_xmdf.tcl
ddr3_128\ipcore_dir\coregen.cgp
ddr3_128\ipcore_dir\mig.prj
ddr3_128\ipcore_dir\mig_39_2\docs\ug388.pdf
ddr3_128\ipcore_dir\mig_39_2\example_design\datasheet.txt
ddr3_128\ipcore_dir\mig_39_2\example_design\log.txt
ddr3_128\ipcore_dir\mig_39_2\example_design\mig.prj
ddr3_128\ipcore_dir\mig_39_2\example_design\modesim\afifo.v
ddr3_128\ipcore_dir\mig_39_2\example_design\modesim\cmd_gen.v
ddr3_128\ipcore_dir\mig_39_2\example_design\modesim\cmd_prbs_gen.v
ddr3_128\ipcore_dir\mig_39_2\example_design\modesim\data_prbs_gen.v
ddr3_128\ipcore_dir\mig_39_2\example_design\modesim\ddr3_128.cr.mti
ddr3_128\ipcore_dir\mig_39_2\example_design\modesim\ddr3_128.mpf
ddr3_128\ipcore_dir\mig_39_2\example_design\modesim\ddr3_model_c3.v
ddr3_128\ipcore_dir\mig_39_2\example_design\modesim\ddr3_model_parameters_c3.vh
ddr3_128\ipcore_dir\mig_39_2\example_design\modesim\example_top.v
ddr3_128\ipcore_dir\mig_39_2\example_design\modesim\infrastructure.v

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