Altera DE1 platform digital password lock design, can drive VGA display

digital_lock_vga_display
digital_lock_vga_display\.qsys_edit
digital_lock_vga_display\.qsys_edit\filters.xml
digital_lock_vga_display\.qsys_edit\preferences.xml
digital_lock_vga_display\address_convertor.v
digital_lock_vga_display\c5_pin_model_dump.txt
digital_lock_vga_display\data_convertor.v
digital_lock_vga_display\db
digital_lock_vga_display\db\.cmp.kpt
digital_lock_vga_display\db\altsyncram_00h1.tdf
digital_lock_vga_display\db\decode_3na.tdf
digital_lock_vga_display\db\digital_lock.asm.qmsg
digital_lock_vga_display\db\digital_lock.asm.rdb
digital_lock_vga_display\db\digital_lock.cbx.xml
digital_lock_vga_display\db\digital_lock.cmp.ammdb
digital_lock_vga_display\db\digital_lock.cmp.bpm
digital_lock_vga_display\db\digital_lock.cmp.cdb
digital_lock_vga_display\db\digital_lock.cmp.hdb
digital_lock_vga_display\db\digital_lock.cmp.idb
digital_lock_vga_display\db\digital_lock.cmp.logdb
digital_lock_vga_display\db\digital_lock.cmp.rdb
digital_lock_vga_display\db\digital_lock.cmp_merge.kpt
digital_lock_vga_display\db\digital_lock.cyclonev_io_sim_cache.ff_0c_fast.hsd
digital_lock_vga_display\db\digital_lock.cyclonev_io_sim_cache.ff_85c_fast.hsd
digital_lock_vga_display\db\digital_lock.cyclonev_io_sim_cache.tt_0c_slow.hsd
digital_lock_vga_display\db\digital_lock.cyclonev_io_sim_cache.tt_85c_slow.hsd
digital_lock_vga_display\db\digital_lock.db_info
digital_lock_vga_display\db\digital_lock.eda.qmsg
digital_lock_vga_display\db\digital_lock.fit.qmsg
digital_lock_vga_display\db\digital_lock.hier_info
digital_lock_vga_display\db\digital_lock.hif
digital_lock_vga_display\db\digital_lock.lpc.html
digital_lock_vga_display\db\digital_lock.lpc.rdb
digital_lock_vga_display\db\digital_lock.lpc.txt
digital_lock_vga_display\db\digital_lock.map.ammdb
digital_lock_vga_display\db\digital_lock.map.bpm
digital_lock_vga_display\db\digital_lock.map.cdb
digital_lock_vga_display\db\digital_lock.map.hdb
digital_lock_vga_display\db\digital_lock.map.kpt
digital_lock_vga_display\db\digital_lock.map.logdb
digital_lock_vga_display\db\digital_lock.map.qmsg
digital_lock_vga_display\db\digital_lock.map.rdb
digital_lock_vga_display\db\digital_lock.map_bb.cdb
digital_lock_vga_display\db\digital_lock.map_bb.hdb
digital_lock_vga_display\db\digital_lock.map_bb.logdb
digital_lock_vga_display\db\digital_lock.npp.qmsg
digital_lock_vga_display\db\digital_lock.pplq.rdb
digital_lock_vga_display\db\digital_lock.pre_map.hdb
digital_lock_vga_display\db\digital_lock.pti_db_list.ddb
digital_lock_vga_display\db\digital_lock.root_partition.map.reg_db.cdb
digital_lock_vga_display\db\digital_lock.routing.rdb
digital_lock_vga_display\db\digital_lock.rtlv.hdb
digital_lock_vga_display\db\digital_lock.rtlv_sg.cdb
digital_lock_vga_display\db\digital_lock.rtlv_sg_swap.cdb
digital_lock_vga_display\db\digital_lock.sgate.nvd
digital_lock_vga_display\db\digital_lock.sgate_sm.nvd
digital_lock_vga_display\db\digital_lock.sgate_sm_bdd.nvd
digital_lock_vga_display\db\digital_lock.sld_design_entry.sci
digital_lock_vga_display\db\digital_lock.sld_design_entry_dsc.sci
digital_lock_vga_display\db\digital_lock.smart_action.txt
digital_lock_vga_display\db\digital_lock.smp_dump.txt
digital_lock_vga_display\db\digital_lock.sta.qmsg
digital_lock_vga_display\db\digital_lock.sta.rdb
digital_lock_vga_display\db\digital_lock.sta_cmp.6_slow_1100mv_85c.tdb
digital_lock_vga_display\db\digital_lock.tiscmp.fast_1100mv_0c.ddb
digital_lock_vga_display\db\digital_lock.tiscmp.fast_1100mv_85c.ddb
digital_lock_vga_display\db\digital_lock.tiscmp.slow_1100mv_0c.ddb
digital_lock_vga_display\db\digital_lock.tiscmp.slow_1100mv_85c.ddb
digital_lock_vga_display\db\digital_lock.tis_db_list.ddb
digital_lock_vga_display\db\digital_lock.tmw_info
digital_lock_vga_display\db\digital_lock.vpr.ammdb
digital_lock_vga_display\db\digital_lock_partition_pins.json
digital_lock_vga_display\db\mux_jhb.tdf
digital_lock_vga_display\db\prev_cmp_digital_lock.qmsg
digital_lock_vga_display\digital_lock.qpf
digital_lock_vga_display\digital_lock.qsf
digital_lock_vga_display\digital_lock.qws
digital_lock_vga_display\digital_lock.v
digital_lock_vga_display\digital_lock.v.bak
digital_lock_vga_display\executable.v
digital_lock_vga_display\executable.v.bak
digital_lock_vga_display\fsm.v
digital_lock_vga_display\fsm.v.bak
digital_lock_vga_display\greybox_tmp
digital_lock_vga_display\greybox_tmp\cbx_args.txt
digital_lock_vga_display\incremental_db
digital_lock_vga_display\incremental_db\compiled_partitions
digital_lock_vga_display\incremental_db\compiled_partitions\digital_lock.db_info
digital_lock_vga_display\incremental_db\compiled_partitions\digital_lock.root_partition.cmp.ammdb
digital_lock_vga_display\incremental_db\compiled_partitions\digital_lock.root_partition.cmp.cdb
digital_lock_vga_display\incremental_db\compiled_partitions\digital_lock.root_partition.cmp.dfp
digital_lock_vga_display\incremental_db\compiled_partitions\digital_lock.root_partition.cmp.hbdb.cdb
digital_lock_vga_display\incremental_db\compiled_partitions\digital_lock.root_partition.cmp.hbdb.hdb
digital_lock_vga_display\incremental_db\compiled_partitions\digital_lock.root_partition.cmp.hbdb.sig
digital_lock_vga_display\incremental_db\compiled_partitions\digital_lock.root_partition.cmp.hdb
digital_lock_vga_display\incremental_db\compiled_partitions\digital_lock.root_partition.cmp.logdb
digital_lock_vga_display\incremental_db\compiled_partitions\digital_lock.root_partition.cmp.rcfdb
digital_lock_vga_display\incremental_db\compiled_partitions\digital_lock.root_partition.map.cdb
digital_lock_vga_display\incremental_db\compiled_partitions\digital_lock.root_partition.map.dpi
digital_lock_vga_display\incremental_db\compiled_partitions\digital_lock.root_partition.map.hbdb.cdb

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