Complete the SDRAM power-on configuration, the state machine to write its read-write module, memory module, and through two asynchronous as a storage and read the channel

sdram_ip\dcfifo_ctrl.v
sdram_ip\dcfifo_ctrl.v.bak
sdram_ip\rdfifo.bsf
sdram_ip\rdfifo.qip
sdram_ip\rdfifo.v
sdram_ip\rdfifo_wave0.jpg
sdram_ip\sdbank_switch.v
sdram_ip\sdbank_switch.v.bak
sdram_ip\sdram_2fifo_top.v
sdram_ip\sdram_2fifo_top.v.bak
sdram_ip\sdram_cmd.v
sdram_ip\sdram_cmd.v.bak
sdram_ip\sdram_ctrl.v
sdram_ip\sdram_ctrl.v.bak
sdram_ip\sdram_para.v
sdram_ip\sdram_top.v
sdram_ip\sdram_top.v.bak
sdram_ip\sdram_wr_data.v
sdram_ip\sdram_wr_data.v.bak
sdram_ip\wrfifo.bsf
sdram_ip\wrfifo.qip
sdram_ip\wrfifo.v
sdram_ip\wrfifo_wave0.jpg
sdram_ip

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