Verilog realizes master slave control on AHB bus and verifies it on FPGA

ahb_sdr\tb\mt48lc4m32b2.v
ahb_sdr\tb\tb_sdr.v
ahb_sdr\src\verilog\ahb_sdrctrl.v
ahb_sdr\src\verilog\defines.v
ahb_sdr\sim\modelSim\sim_gui.bat
ahb_sdr\sim\modelSim\sim.do
ahb_sdr\sim\modelSim\transcript
ahb_sdr\sim\modelSim\signal.f
ahb_sdr\doc\design\Thumbs.db
ahb_sdr\src\vhdl
ahb_sdr\src\verilog
ahb_sdr\sim\modelSim
ahb_sdr\sim\vcs
ahb_sdr\syn\synopsys
ahb_sdr\syn\ise
ahb_sdr\syn\synplify
ahb_sdr\doc\verification
ahb_sdr\doc\design
ahb_sdr\tb
ahb_sdr\c
ahb_sdr\src
ahb_sdr\sim
ahb_sdr\syn
ahb_sdr\doc
ahb_sdr

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