The connection relation of the gate level circuit of 4Bit carry adder is described in Verilog language with the method of gate level netlist

4Bit超前进位加法器门级电路设计与仿真\add.v
4Bit超前进位加法器门级电路设计与仿真\cell.v
4Bit超前进位加法器门级电路设计与仿真\tb.v
4Bit超前进位加法器门级电路设计与仿真\仿真截图2.jpg
4Bit超前进位加法器门级电路设计与仿真\设计报告.docx
4Bit超前进位加法器门级电路设计与仿真

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