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新建 WinRAR ZIP 压缩文件
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Category :
VHDL-FPGA-Verilog
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Update : 2017-11-06
Size : 290kb
Downloaded :0次
Author :
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Introduction - If you have any usage issues, please Google them yourself
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Asynchronous FIFO and I2C bus controller for cross clock domain data transmission.
Packet file list
(Preview for download)
asy_FIFO
asy_FIFO\asy_FIFO.qpf
asy_FIFO\asy_FIFO.qsf
asy_FIFO\asy_FIFO.qws
asy_FIFO\asy_FIFO.v
asy_FIFO\asy_FIFO.v.bak
asy_FIFO\asy_FIFO_assignment_defaults.qdf
asy_FIFO\db
asy_FIFO\db\asy_FIFO.db_info
asy_FIFO\db\asy_FIFO.ipinfo
asy_FIFO\db\asy_FIFO.sim.vwf
asy_FIFO\db\asy_FIFO.sld_design_entry.sci
asy_FIFO\db\logic_util_heursitic.dat
asy_FIFO\db\prev_cmp_asy_FIFO.qmsg
asy_FIFO\incremental_db
asy_FIFO\incremental_db\compiled_partitions
asy_FIFO\incremental_db\compiled_partitions\asy_FIFO.db_info
asy_FIFO\incremental_db\README
asy_FIFO\output_files
asy_FIFO\output_files\asy_FIFO.asm.rpt
asy_FIFO\output_files\asy_FIFO.done
asy_FIFO\output_files\asy_FIFO.eda.rpt
asy_FIFO\output_files\asy_FIFO.fit.rpt
asy_FIFO\output_files\asy_FIFO.fit.smsg
asy_FIFO\output_files\asy_FIFO.fit.summary
asy_FIFO\output_files\asy_FIFO.flow.rpt
asy_FIFO\output_files\asy_FIFO.jdi
asy_FIFO\output_files\asy_FIFO.map.rpt
asy_FIFO\output_files\asy_FIFO.map.summary
asy_FIFO\output_files\asy_FIFO.pin
asy_FIFO\output_files\asy_FIFO.pof
asy_FIFO\output_files\asy_FIFO.sim.rpt
asy_FIFO\output_files\asy_FIFO.sof
asy_FIFO\output_files\asy_FIFO.sta.rpt
asy_FIFO\output_files\asy_FIFO.sta.summary
asy_FIFO\simulation
asy_FIFO\simulation\modelsim
asy_FIFO\simulation\modelsim\asy_FIFO.sft
asy_FIFO\simulation\modelsim\asy_FIFO.vo
asy_FIFO\simulation\modelsim\asy_FIFO_8_1200mv_0c_slow.vo
asy_FIFO\simulation\modelsim\asy_FIFO_8_1200mv_0c_v_slow.sdo
asy_FIFO\simulation\modelsim\asy_FIFO_8_1200mv_85c_slow.vo
asy_FIFO\simulation\modelsim\asy_FIFO_8_1200mv_85c_v_slow.sdo
asy_FIFO\simulation\modelsim\asy_FIFO_fast.vo
asy_FIFO\simulation\modelsim\asy_FIFO_min_1200mv_0c_fast.vo
asy_FIFO\simulation\modelsim\asy_FIFO_min_1200mv_0c_v_fast.sdo
asy_FIFO\simulation\modelsim\asy_FIFO_modelsim.xrf
asy_FIFO\simulation\modelsim\asy_FIFO_v.sdo
asy_FIFO\simulation\modelsim\asy_FIFO_v_fast.sdo
asy_FIFO\simulation\qsim
asy_FIFO\simulation\qsim\asy_FIFO.do
asy_FIFO\simulation\qsim\asy_FIFO.sim.vwf
asy_FIFO\simulation\qsim\asy_FIFO.vo
asy_FIFO\simulation\qsim\asy_FIFO.vt
asy_FIFO\simulation\qsim\asy_FIFO_v.sdo
asy_FIFO\Waveform.vwf
asy_FIFO\Waveform.vwf.temp
i2c
i2c\db
i2c\db\i2c.cbx.xml
i2c\db\i2c.cmp.rdb
i2c\db\i2c.db_info
i2c\db\i2c.ipinfo
i2c\db\i2c.map.qmsg
i2c\db\i2c.map.rdb
i2c\db\i2c.map_bb.hdb
i2c\db\i2c.pti_db_list.ddb
i2c\db\i2c.sld_design_entry.sci
i2c\db\i2c.smart_action.txt
i2c\db\i2c.tis_db_list.ddb
i2c\db\logic_util_heursitic.dat
i2c\db\prev_cmp_i2c.qmsg
i2c\EEPROM.v
i2c\EEPROM.v.bak
i2c\EEPROM_WR.v
i2c\EEPROM_WR.v.bak
i2c\i2c.cr.mti
i2c\i2c.mpf
i2c\i2c.qpf
i2c\i2c.qsf
i2c\i2c.qws
i2c\i2c.v
i2c\i2c.v.bak
i2c\output_files
i2c\output_files\i2c.flow.rpt
i2c\output_files\i2c.map.rpt
i2c\output_files\i2c.map.summary
i2c\signal.v
i2c\signal.v.bak
i2c\work
i2c\work\_info
i2c\work\_temp
i2c\work\_temp\vlog25j7h4
i2c\work\_temp\vlog6eb75h
i2c\work\_temp\vlog9a1652
i2c\work\_temp\vlogmx7z8x
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