After sending one byte over SPI, you have to clear one byte in the data register (DR) again. In SPI you always send and receive a byte You cannot just send OR receive a byte, it's always AND. The technical explanation is that there is only one clock line, and two data lines (MISO and MOSI)

Fujitsu\Utility
Fujitsu\Samples
Fujitsu\README.TXT
Fujitsu\Fuj_prg.pdf
Fujitsu\AccelEDA - [Sheet1].pdf
Fujitsu\Fuj_prg_doc.pdf
Fujitsu\Utility\Utility.zip
Fujitsu\Samples\90595.ZIP

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