A digital clock is designed with Verilog language, and it can run successfully on board

clock
clock\clock.qpf
clock\clock.qsf
clock\clock.qws
clock\clock.v
clock\clock.v.bak
clock\counter.v
clock\counter.v.bak
clock\db
clock\db\.cmp.kpt
clock\db\clock.asm.qmsg
clock\db\clock.asm.rdb
clock\db\clock.cbx.xml
clock\db\clock.cmp.idb
clock\db\clock.cmp.rdb
clock\db\clock.cmp_merge.kpt
clock\db\clock.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
clock\db\clock.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
clock\db\clock.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
clock\db\clock.db_info
clock\db\clock.eda.qmsg
clock\db\clock.fit.qmsg
clock\db\clock.hier_info
clock\db\clock.hif
clock\db\clock.ipinfo
clock\db\clock.lpc.html
clock\db\clock.lpc.rdb
clock\db\clock.lpc.txt
clock\db\clock.map.ammdb
clock\db\clock.map.bpm
clock\db\clock.map.cdb
clock\db\clock.map.hdb
clock\db\clock.map.kpt
clock\db\clock.map.logdb
clock\db\clock.map.qmsg
clock\db\clock.map.rdb
clock\db\clock.map_bb.cdb
clock\db\clock.map_bb.hdb
clock\db\clock.map_bb.logdb
clock\db\clock.pplq.rdb
clock\db\clock.pre_map.hdb
clock\db\clock.pti_db_list.ddb
clock\db\clock.root_partition.map.reg_db.cdb
clock\db\clock.routing.rdb
clock\db\clock.rtlv.hdb
clock\db\clock.rtlv_sg.cdb
clock\db\clock.rtlv_sg_swap.cdb
clock\db\clock.sgdiff.cdb
clock\db\clock.sgdiff.hdb
clock\db\clock.sld_design_entry.sci
clock\db\clock.sld_design_entry_dsc.sci
clock\db\clock.smart_action.txt
clock\db\clock.sta.qmsg
clock\db\clock.sta.rdb
clock\db\clock.stingray_io_sim_cache.99um_ff_1200mv_0c_fast.hsd
clock\db\clock.stingray_io_sim_cache.99um_tt_1200mv_0c_slow.hsd
clock\db\clock.stingray_io_sim_cache.99um_tt_1200mv_85c_slow.hsd
clock\db\clock.tis_db_list.ddb
clock\db\clock.tiscmp.fast_1200mv_0c.ddb
clock\db\clock.tiscmp.fastest_slow_1200mv_0c.ddb
clock\db\clock.tiscmp.fastest_slow_1200mv_85c.ddb
clock\db\clock.tiscmp.slow_1200mv_0c.ddb
clock\db\clock.tiscmp.slow_1200mv_85c.ddb
clock\db\clock.tmw_info
clock\db\clock.vpr.ammdb
clock\db\logic_util_heursitic.dat
clock\db\prev_cmp_clock.qmsg
clock\fenpin.v
clock\fenpin.v.bak
clock\incremental_db
clock\incremental_db\README
clock\incremental_db\compiled_partitions
clock\incremental_db\compiled_partitions\clock.db_info
clock\incremental_db\compiled_partitions\clock.root_partition.cmp.ammdb
clock\incremental_db\compiled_partitions\clock.root_partition.cmp.cdb
clock\incremental_db\compiled_partitions\clock.root_partition.cmp.dfp
clock\incremental_db\compiled_partitions\clock.root_partition.cmp.hdb
clock\incremental_db\compiled_partitions\clock.root_partition.cmp.logdb
clock\incremental_db\compiled_partitions\clock.root_partition.cmp.rcfdb
clock\incremental_db\compiled_partitions\clock.root_partition.map.cdb
clock\incremental_db\compiled_partitions\clock.root_partition.map.dpi
clock\incremental_db\compiled_partitions\clock.root_partition.map.hbdb.cdb
clock\incremental_db\compiled_partitions\clock.root_partition.map.hbdb.hb_info
clock\incremental_db\compiled_partitions\clock.root_partition.map.hbdb.hdb
clock\incremental_db\compiled_partitions\clock.root_partition.map.hbdb.sig
clock\incremental_db\compiled_partitions\clock.root_partition.map.hdb
clock\incremental_db\compiled_partitions\clock.root_partition.map.kpt
clock\output_files
clock\output_files\clock.asm.rpt
clock\output_files\clock.done
clock\output_files\clock.eda.rpt
clock\output_files\clock.fit.rpt
clock\output_files\clock.fit.smsg
clock\output_files\clock.fit.summary
clock\output_files\clock.flow.rpt
clock\output_files\clock.jdi
clock\output_files\clock.map.rpt
clock\output_files\clock.map.smsg
clock\output_files\clock.map.summary
clock\output_files\clock.pin

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