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VHDL-FPGA-Verilog
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Update : 2017-11-15
Size : 6.47mb
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Introduction - If you have any usage issues, please Google them yourself
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Using Verilog hardware description language written in AD sampling module, I hope useful for everyone
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adc\ad_module.pti_db_list.ddb
adc\ad_module.qpf
adc\ad_module.qsf
adc\ad_module.qws
adc\ad_module.tis_db_list.ddb
adc\ad_module.v
adc\ad_module.v.bak
adc\ad_top.qpf
adc\ad_top.qsf
adc\ad_top.qsf.bak
adc\ad_top.qws
adc\ad_top.v
adc\ad_top.v.bak
adc\db\.cmp.kpt
adc\db\ad_module.ace_cmp.bpm
adc\db\ad_module.ace_cmp.cdb
adc\db\ad_module.ace_cmp.hdb
adc\db\ad_module.asm.qmsg
adc\db\ad_module.asm.rdb
adc\db\ad_module.asm_labs.ddb
adc\db\ad_module.cbx.xml
adc\db\ad_module.cmp.bpm
adc\db\ad_module.cmp.cdb
adc\db\ad_module.cmp.hdb
adc\db\ad_module.cmp.idb
adc\db\ad_module.cmp.logdb
adc\db\ad_module.cmp.rdb
adc\db\ad_module.cmp_merge.kpt
adc\db\ad_module.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
adc\db\ad_module.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
adc\db\ad_module.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
adc\db\ad_module.db_info
adc\db\ad_module.eco.cdb
adc\db\ad_module.eda.qmsg
adc\db\ad_module.fit.qmsg
adc\db\ad_module.hier_info
adc\db\ad_module.hif
adc\db\ad_module.ipinfo
adc\db\ad_module.lpc.html
adc\db\ad_module.lpc.rdb
adc\db\ad_module.lpc.txt
adc\db\ad_module.map.ammdb
adc\db\ad_module.map.bpm
adc\db\ad_module.map.cdb
adc\db\ad_module.map.hdb
adc\db\ad_module.map.kpt
adc\db\ad_module.map.logdb
adc\db\ad_module.map.qmsg
adc\db\ad_module.map.rdb
adc\db\ad_module.map_bb.cdb
adc\db\ad_module.map_bb.hdb
adc\db\ad_module.map_bb.logdb
adc\db\ad_module.pre_map.hdb
adc\db\ad_module.pti_db_list.ddb
adc\db\ad_module.root_partition.map.reg_db.cdb
adc\db\ad_module.routing.rdb
adc\db\ad_module.rtlv.hdb
adc\db\ad_module.rtlv_sg.cdb
adc\db\ad_module.rtlv_sg_swap.cdb
adc\db\ad_module.sgdiff.cdb
adc\db\ad_module.sgdiff.hdb
adc\db\ad_module.sld_design_entry.sci
adc\db\ad_module.sld_design_entry_dsc.sci
adc\db\ad_module.smart_action.txt
adc\db\ad_module.smp_dump.txt
adc\db\ad_module.sta.qmsg
adc\db\ad_module.sta.rdb
adc\db\ad_module.sta_cmp.8_slow_1200mv_85c.tdb
adc\db\ad_module.tiscmp.fastest_slow_1200mv_0c.ddb
adc\db\ad_module.tiscmp.fastest_slow_1200mv_85c.ddb
adc\db\ad_module.tiscmp.fast_1200mv_0c.ddb
adc\db\ad_module.tiscmp.slow_1200mv_0c.ddb
adc\db\ad_module.tiscmp.slow_1200mv_85c.ddb
adc\db\ad_module.tis_db_list.ddb
adc\db\ad_module.tmw_info
adc\db\ad_module.vpr.ammdb
adc\db\ad_top.ace_cmp.bpm
adc\db\ad_top.ace_cmp.cdb
adc\db\ad_top.ace_cmp.hdb
adc\db\ad_top.asm.qmsg
adc\db\ad_top.asm.rdb
adc\db\ad_top.asm_labs.ddb
adc\db\ad_top.cbx.xml
adc\db\ad_top.cmp.bpm
adc\db\ad_top.cmp.cdb
adc\db\ad_top.cmp.hdb
adc\db\ad_top.cmp.idb
adc\db\ad_top.cmp.logdb
adc\db\ad_top.cmp.rdb
adc\db\ad_top.cmp_merge.kpt
adc\db\ad_top.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
adc\db\ad_top.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
adc\db\ad_top.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
adc\db\ad_top.db_info
adc\db\ad_top.eco.cdb
adc\db\ad_top.eda.qmsg
adc\db\ad_top.fit.qmsg
adc\db\ad_top.hier_info
adc\db\ad_top.hif
adc\db\ad_top.ipinfo
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