Using Verilog hardware description language to write the key circuit module, I hope to help you!

A4_Key1\A4_Key1.qpf
A4_Key1\A4_Key1.qsf
A4_Key1\A4_Key1.v
A4_Key1\A4_Key1.v.bak
A4_Key1\db\.cmp.kpt
A4_Key1\db\A4_Key1.ace_cmp.bpm
A4_Key1\db\A4_Key1.ace_cmp.cdb
A4_Key1\db\A4_Key1.ace_cmp.hdb
A4_Key1\db\A4_Key1.asm.qmsg
A4_Key1\db\A4_Key1.asm.rdb
A4_Key1\db\A4_Key1.asm_labs.ddb
A4_Key1\db\A4_Key1.cbx.xml
A4_Key1\db\A4_Key1.cmp.bpm
A4_Key1\db\A4_Key1.cmp.cdb
A4_Key1\db\A4_Key1.cmp.hdb
A4_Key1\db\A4_Key1.cmp.idb
A4_Key1\db\A4_Key1.cmp.logdb
A4_Key1\db\A4_Key1.cmp.rdb
A4_Key1\db\A4_Key1.cmp_merge.kpt
A4_Key1\db\A4_Key1.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
A4_Key1\db\A4_Key1.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
A4_Key1\db\A4_Key1.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
A4_Key1\db\A4_Key1.db_info
A4_Key1\db\A4_Key1.eco.cdb
A4_Key1\db\A4_Key1.eda.qmsg
A4_Key1\db\A4_Key1.fit.qmsg
A4_Key1\db\A4_Key1.hier_info
A4_Key1\db\A4_Key1.hif
A4_Key1\db\A4_Key1.ipinfo
A4_Key1\db\A4_Key1.lpc.html
A4_Key1\db\A4_Key1.lpc.rdb
A4_Key1\db\A4_Key1.lpc.txt
A4_Key1\db\A4_Key1.map.ammdb
A4_Key1\db\A4_Key1.map.bpm
A4_Key1\db\A4_Key1.map.cdb
A4_Key1\db\A4_Key1.map.hdb
A4_Key1\db\A4_Key1.map.kpt
A4_Key1\db\A4_Key1.map.logdb
A4_Key1\db\A4_Key1.map.qmsg
A4_Key1\db\A4_Key1.map.rdb
A4_Key1\db\A4_Key1.map_bb.cdb
A4_Key1\db\A4_Key1.map_bb.hdb
A4_Key1\db\A4_Key1.map_bb.logdb
A4_Key1\db\A4_Key1.pplq.rdb
A4_Key1\db\A4_Key1.pre_map.hdb
A4_Key1\db\A4_Key1.pti_db_list.ddb
A4_Key1\db\A4_Key1.root_partition.map.reg_db.cdb
A4_Key1\db\A4_Key1.routing.rdb
A4_Key1\db\A4_Key1.rtlv.hdb
A4_Key1\db\A4_Key1.rtlv_sg.cdb
A4_Key1\db\A4_Key1.rtlv_sg_swap.cdb
A4_Key1\db\A4_Key1.sgdiff.cdb
A4_Key1\db\A4_Key1.sgdiff.hdb
A4_Key1\db\A4_Key1.sld_design_entry.sci
A4_Key1\db\A4_Key1.sld_design_entry_dsc.sci
A4_Key1\db\A4_Key1.smart_action.txt
A4_Key1\db\A4_Key1.sta.qmsg
A4_Key1\db\A4_Key1.sta.rdb
A4_Key1\db\A4_Key1.sta_cmp.8_slow_1200mv_85c.tdb
A4_Key1\db\A4_Key1.tiscmp.fastest_slow_1200mv_0c.ddb
A4_Key1\db\A4_Key1.tiscmp.fastest_slow_1200mv_85c.ddb
A4_Key1\db\A4_Key1.tiscmp.fast_1200mv_0c.ddb
A4_Key1\db\A4_Key1.tiscmp.slow_1200mv_0c.ddb
A4_Key1\db\A4_Key1.tiscmp.slow_1200mv_85c.ddb
A4_Key1\db\A4_Key1.tis_db_list.ddb
A4_Key1\db\A4_Key1.vpr.ammdb
A4_Key1\db\logic_util_heursitic.dat
A4_Key1\db\prev_cmp_A4_Key1.qmsg
A4_Key1\incremental_db\compiled_partitions\A4_Key1.db_info
A4_Key1\incremental_db\compiled_partitions\A4_Key1.root_partition.cmp.ammdb
A4_Key1\incremental_db\compiled_partitions\A4_Key1.root_partition.cmp.cdb
A4_Key1\incremental_db\compiled_partitions\A4_Key1.root_partition.cmp.dfp
A4_Key1\incremental_db\compiled_partitions\A4_Key1.root_partition.cmp.hdb
A4_Key1\incremental_db\compiled_partitions\A4_Key1.root_partition.cmp.logdb
A4_Key1\incremental_db\compiled_partitions\A4_Key1.root_partition.cmp.rcfdb
A4_Key1\incremental_db\compiled_partitions\A4_Key1.root_partition.map.cdb
A4_Key1\incremental_db\compiled_partitions\A4_Key1.root_partition.map.dpi
A4_Key1\incremental_db\compiled_partitions\A4_Key1.root_partition.map.hbdb.cdb
A4_Key1\incremental_db\compiled_partitions\A4_Key1.root_partition.map.hbdb.hb_info
A4_Key1\incremental_db\compiled_partitions\A4_Key1.root_partition.map.hbdb.hdb
A4_Key1\incremental_db\compiled_partitions\A4_Key1.root_partition.map.hbdb.sig
A4_Key1\incremental_db\compiled_partitions\A4_Key1.root_partition.map.hdb
A4_Key1\incremental_db\compiled_partitions\A4_Key1.root_partition.map.kpt
A4_Key1\incremental_db\README
A4_Key1\output_files\A4_Key1.asm.rpt
A4_Key1\output_files\A4_Key1.done
A4_Key1\output_files\A4_Key1.eda.rpt
A4_Key1\output_files\A4_Key1.fit.rpt
A4_Key1\output_files\A4_Key1.fit.smsg
A4_Key1\output_files\A4_Key1.fit.summary
A4_Key1\output_files\A4_Key1.flow.rpt
A4_Key1\output_files\A4_Key1.jdi
A4_Key1\output_files\A4_Key1.map.rpt
A4_Key1\output_files\A4_Key1.map.summary
A4_Key1\output_files\A4_Key1.pin
A4_Key1\output_files\A4_Key1.sof
A4_Key1\output_files\A4_Key1.sta.rpt
A4_Key1\output_files\A4_Key1.sta.summary
A4_Key1\simulation\modelsim\A4_Key1.sft
A4_Key1\simulation\modelsim\A4_Key1.vo

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