spi Serial and parallel conversion

spi

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Category : VHDL-FPGA-Verilog
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Update : 2017-11-24
Size : 83kb
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Serial and parallel conversion

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Filename	Size	Update
spi\aa\0aa.mgf	254374	2017-11-23
spi\aa\1aa.mgf	43670	2017-11-23
spi\aa\2aa.mgf	6790	2017-11-23
spi\aa\3aa.mgf	22726	2017-11-23
spi\aa\aa.adf	1270	2017-11-23
spi\aa\aa.LIB	2699	2017-11-23
spi\aa\aa.rlb	354	2017-11-23
spi\aa\aa.wsp	4875	2017-11-23
spi\aa\aa_0.rep	67320	2017-11-23
spi\aa\bde.set	1802	2017-11-22
spi\aa\compilation.order	139	2017-11-23
spi\aa\compile\aa.epr	159	2017-11-23
spi\aa\compile\aa.erf	860	2017-11-23
spi\aa\compile\aa.opt	422	2017-11-23
spi\aa\compile\aa.opv	170	2017-11-23
spi\aa\compile\contents.lib~aa	553	2017-11-23
spi\aa\compile\spi_interf.bdeid	484	2017-11-23
spi\aa\compile\spi_interf.v	1628	2017-11-23
spi\aa\compile\vcp_cmd.log	749	2017-11-23
spi\aa\compile.cfg	481	2017-11-23
spi\aa\Edfmap.ini	19585	2011-10-10
spi\aa\log\console.log	16801	2017-11-23
spi\aa\log\spi_interf.htm	3775	2017-11-23
spi\aa\projlib.cfg	30	2017-11-22
spi\aa\src\spi_adr.v	1342	2017-11-23
spi\aa\src\spi_ctrl.v	1662	2017-11-23
spi\aa\src\spi_interf.bak	25123	2017-11-23
spi\aa\src\spi_interf.bde	28361	2017-11-23
spi\aa\src\spi_rcve_cnt.v.bak	1097	2017-11-22
spi\aa\src\spi_toBus.v	1173	2017-11-22
spi\aa\src\TestBench\spi_adr_TB.v	1165	2017-11-23
spi\aa\src\TestBench\spi_adr_TB.v.bak	1079	2017-11-22
spi\aa\src\TestBench\spi_adr_TB_runtest.do	323	2017-11-23
spi\aa\src\TestBench\spi_adr_TB_settings.txt	622	2017-11-23
spi\aa\src\TestBench\spi_interf_TB.v	1613	2017-11-23
spi\aa\src\TestBench\spi_interf_TB_runtest.do	324	2017-11-23
spi\aa\src\TestBench\spi_interf_TB_settings.txt	639	2017-11-23
spi\aa\stimulators.set	158	2017-11-23
spi\aa\synthesis.order	182	2017-11-23
spi\library.cfg	64	2017-11-22
spi\spi.aws	127	2017-11-23
spi\spi.wsw	1014	2017-11-23
spi\aa\src\TestBench
spi\aa\compile
spi\aa\log
spi\aa\src
spi\aa
spi

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