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  • Category : VHDL-FPGA-Verilog
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  • Update : 2017-12-06
  • Size : 116kb
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  • Author :fy5****
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Basys2 development board introductory tutorial experiment Leb1 source code, switch and key control light emitting tube
Packet file list
(Preview for download)
FilenameSizeUpdate
lab1\iseconfig\lab1.projectmgr 5849 2017-12-06
lab1\iseconfig\TOP_FY.xreport 20427 2017-12-06
lab1\lab1.gise 12003 2017-12-06
lab1\lab1.xise 41236 2017-12-06
lab1\myufc.ucf 761 2017-12-06
lab1\par_usage_statistics.html 4133 2017-12-06
lab1\top_fy.bgn 6964 2017-12-06
lab1\top_fy.bit 1484496 2017-12-06
lab1\TOP_FY.bld 987 2017-12-06
lab1\TOP_FY.cmd_log 1656 2017-12-06
lab1\top_fy.drc 188 2017-12-06
lab1\TOP_FY.lso 6 2017-12-06
lab1\TOP_FY.ncd 8850 2017-12-06
lab1\TOP_FY.ngc 5956 2017-12-06
lab1\TOP_FY.ngd 10839 2017-12-06
lab1\TOP_FY.ngr 2755 2017-12-06
lab1\TOP_FY.pad 19979 2017-12-06
lab1\TOP_FY.par 5551 2017-12-06
lab1\TOP_FY.pcf 1772 2017-12-06
lab1\TOP_FY.prj 24 2017-12-06
lab1\TOP_FY.ptwx 16463 2017-12-06
lab1\TOP_FY.stx
lab1\TOP_FY.syr 9828 2017-12-06
lab1\TOP_FY.twr 2415 2017-12-06
lab1\TOP_FY.twx 19737 2017-12-06
lab1\TOP_FY.unroutes 159 2017-12-06
lab1\TOP_FY.ut 552 2017-12-06
lab1\TOP_FY.vhd 1292 2017-12-06
lab1\TOP_FY.xpi 46 2017-12-06
lab1\TOP_FY.xst 1068 2017-12-06
lab1\TOP_FY_bitgen.xwbt 183 2017-12-06
lab1\TOP_FY_envsettings.html 13329 2017-12-06
lab1\TOP_FY_guide.ncd 8850 2017-12-06
lab1\TOP_FY_map.map 5406 2017-12-06
lab1\TOP_FY_map.mrp 12299 2017-12-06
lab1\TOP_FY_map.ncd 5470 2017-12-06
lab1\TOP_FY_map.ngm 20727 2017-12-06
lab1\TOP_FY_map.xrpt 33753 2017-12-06
lab1\TOP_FY_ngdbuild.xrpt 4964 2017-12-06
lab1\TOP_FY_pad.csv 20011 2017-12-06
lab1\TOP_FY_pad.txt 96236 2017-12-06
lab1\TOP_FY_par.xrpt 227855 2017-12-06
lab1\TOP_FY_summary.html 11164 2017-12-06
lab1\TOP_FY_summary.xml 408 2017-12-06
lab1\TOP_FY_usage.xml 5052 2017-12-06
lab1\TOP_FY_xst.xrpt 10408 2017-12-06
lab1\usage_statistics_webtalk.html 28734 2017-12-06
lab1\webtalk.log 674 2017-12-06
lab1\webtalk_pn.xml 2823 2017-12-06
lab1\xlnx_auto_0_xdb\cst.xbcd 2246 2017-12-06
lab1\xst\work\work.vdbl 2500 2017-12-06
lab1\xst\work\work.vdbx 68 2017-12-06
lab1\_ngo\netlist.lst 35 2017-12-06
lab1\_xmsgs\bitgen.xmsgs 367 2017-12-06
lab1\_xmsgs\map.xmsgs 1454 2017-12-06
lab1\_xmsgs\ngdbuild.xmsgs 367 2017-12-06
lab1\_xmsgs\par.xmsgs 1151 2017-12-06
lab1\_xmsgs\pn_parser.xmsgs 573 2017-12-06
lab1\_xmsgs\trce.xmsgs 1149 2017-12-06
lab1\_xmsgs\xst.xmsgs 367 2017-12-06
lab1\xst\dump.xst\TOP_FY.prj
lab1\xst\dump.xst
lab1\xst\projnav.tmp
lab1\xst\work
lab1\ipcore_dir
lab1\iseconfig
lab1\xlnx_auto_0_xdb
lab1\xst
lab1\_ngo
lab1\_xmsgs
lab1
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