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Module基础全集

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2017-12-18
  • Size : 32kb
  • Downloaded :0次
  • Author :hali*****
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
For example, all kinds of veirlog base code, though not as functional as IP core, can learn a lot
Packet file list
(Preview for download)
FilenameSizeUpdate
alu.v 3130 2017-12-04
Asynchronous_D_FF.v 478 2017-11-13
Counter8.v 637 2017-11-20
decoder.bit 3825892 2017-10-23
decoder.v 1298 2017-10-23
decoder_tb.v 1116 2017-10-23
decoder_xdc.xdc 1426 2017-10-23
display7.bit 3825893 2017-10-23
display7.v 1540 2017-10-23
display7_tb.v 1054 2017-10-23
display7_xdc.xdc 1210 2017-10-23
Divider.v 4998 2017-11-20
encoder83.bit 3825894 2017-10-23
encoder83.v 823 2017-10-23
encoder83_Pri.bit 3825898 2017-10-23
encoder83_Pri.v 1439 2017-10-23
encoder83_Pri_tb.v 1172 2017-10-23
encoder83_Pri_xdc.xdc 1402 2017-10-23
encoder83_tb.v 980 2017-10-23
encoder83_xdc.xdc 1210 2017-10-23
JK_FF.v 825 2017-11-13
Pcreg.v 814 2017-11-27
ram.v 1588 2017-11-27
ram2.v 634 2017-11-27
Regfiles.v 2990 2017-11-27
Selector.v 2294 2017-11-27
Synchronous_D_FF.v 443 2017-11-13
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